Async-Assert / Sync-Deassert Reset

Verilog problems / Sequential Design

What you must build

Assert reset the instant it goes active, but only release it once it has been clean for 2 clock edges — the standard reset architecture for any real design.

Engineers use “Async-Assert / Sync-Deassert Reset” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  async_rst_n,
  output reg sync_rst_n
);

  // Your code here — assert sync_rst_n asynchronously with async_rst_n; release through a 2-flop chain.

endmodule

Why this shows up in interviews

Async-Assert / Sync-Deassert Reset sits under Sequential Design (sequential, cdc). Concept: Reset assertion must reach every flop immediately, even mid-cycle, so it belongs in the sensitivity list itself: always @(posedge clk or negedge async_rst_n) . Release, though, must not land on a clock edge and risk a recovery/removal violation — so deassertion is synchronized through two flops before sync_rst_n ever goes high, exactly like a normal 2-flop CDC chain but seeded by an asynchronous reset instead of a data input.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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