Toggle-Based Pulse Synchronizer

Verilog problems / Sequential Design

What you must build

Cross a single-cycle pulse safely between clock domains by toggle-encoding it — a plain 2-flop level synchronizer would simply miss it if the destination clock is slower.

Engineers use “Toggle-Based Pulse Synchronizer” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  tog_in,
  output reg pulse_out
);

  // Your code here — 2-flop synchronize tog_in, then XOR consecutive synced samples to regenerate a pulse.

endmodule

Why this shows up in interviews

Toggle-Based Pulse Synchronizer sits under Sequential Design (sequential, cdc). Concept: A pulse from another domain can't be trusted to survive a plain level synchronizer, since a fast pulse can come and go between destination clock edges. Toggle-encoding fixes this: the source flips a toggle bit for every pulse instead of pulsing directly (that flip happens upstream and is assumed already done here — tog_in is the toggled signal). The destination double-flops that toggle, then XORs two consecutive synchronized samples: pulse_out <= sync1 ^ sync2 . Because a toggle only ever changes state (never returns to a matching value on its own), this reconstructs exactly one clean pulse per source event, no matter how the clocks relate. Using AND instead of XOR misses every toggle-back-to-0 transition.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ