Auto-Repeat Button

Verilog problems / Sequential Design

What you must build

Fire an immediate pulse the instant a button is pressed, then keep firing repeat pulses at a steady interval for as long as it stays held — the key-repeat behavior behind every keyboard.

Engineers use “Auto-Repeat Button” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  btn,
  output reg pulse
);

  // Your code here — pulse once on the rising edge of btn, then every 3 cycles while it stays held; release resets the timer.

endmodule

Why this shows up in interviews

Auto-Repeat Button sits under Sequential Design (sequential, control). Concept: A fresh press (rising edge, tracked with a registered previous-value comparison) fires one pulse immediately and resets a cycle counter. While the button stays held, that counter counts up and fires another pulse every time it reaches the repeat interval, then resets — releasing the button resets the counter so a later press always starts with a fresh, immediate pulse rather than continuing a stale count. Getting the repeat-interval comparison off by one (checking one cycle too early) makes every repeat fire faster than intended, silently changing the whole timing feel of the interface.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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