CDC Bus Hold Register

Verilog problems / Sequential Design

What you must build

Capture a data bus only on a valid strobe and hold it steady otherwise — never let an unregistered async bus pass straight through to downstream logic.

Engineers use “CDC Bus Hold Register” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  valid,
  input  [7:0] data_in,
  output reg [7:0] data_out
);

  // Your code here — capture data_in into data_out only when valid is high; hold otherwise.

endmodule

Why this shows up in interviews

CDC Bus Hold Register sits under Sequential Design (sequential, cdc, datapath). Concept: A multi-bit bus crossing domains can't just be wired through combinationally — different bits can settle at slightly different times, so any glitch or skew on the source side becomes visible immediately downstream. The fix is to only ever update the output register when a (separately synchronized) valid strobe says the bus is stable: if (valid) data_out <= data_in; , holding the old value the rest of the time. Wiring data_out straight to data_in with no register at all defeats the entire point — every glitch on the input rides straight through.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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