Integrated Clock Gating Cell (ICG)

Verilog problems / Sequential Design

What you must build

The standard cell every low-power design leans on to disable a clock branch without ever producing a runt pulse — a level-sensitive latch, not a plain AND gate.

Engineers use “Integrated Clock Gating Cell (ICG)” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  en,
  output gclk
);

  // Your code here — latch en while clk is LOW (transparent latch), then AND with clk.
  // This is a level-sensitive latch: always @* if(!clk) en_latched=en;

endmodule

Why this shows up in interviews

Integrated Clock Gating Cell (ICG) sits under Sequential Design (combinational, clock-generation, low-power). Concept: A naive gclk = clk & en is dangerous: if en changes while clk happens to be high, the output can glitch mid-pulse, and that glitch can clock a downstream flop at the wrong instant. The real ICG latches en only while clk is low (when it's safe) and holds that value steady through the whole high phase: always @* if(!clk) en_latched=en; assign gclk=clk & en_latched; . Skipping the latch and gating directly with en is the exact bug real clock-gating cells exist to prevent — it looks identical in a waveform viewer for slow, careful test patterns, and only shows the glitch when en toggles at the "wrong" moment.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ