True Dual-Port RAM

Verilog problems / Sequential Design

What you must build

An 8x8 memory with two fully independent read/write ports on the same clock — the structure behind every register file and dual-port block RAM.

Engineers use “True Dual-Port RAM” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  we_a, input [2:0] addr_a, input [7:0] wdata_a, output reg [7:0] rdata_a,
  input  we_b, input [2:0] addr_b, input [7:0] wdata_b, output reg [7:0] rdata_b
);

  // Your code here — 8x8 memory array with two fully independent read/write ports.

endmodule

Why this shows up in interviews

True Dual-Port RAM sits under Sequential Design (sequential, memory). Concept: True dual-port RAM means port A and port B can access any two addresses simultaneously, completely independently: each port gets its own write-enable, address, write-data, and registered read-data, all acting on the same underlying memory array. The bug that defeats the entire point is quietly routing port B's access through port A's address ( mem[addr_a] instead of mem[addr_b] ) — it still compiles, still looks like two ports, but port B can now only ever see whatever port A happens to be pointing at.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ