Async-FIFO Empty Flag Synchronizer

Verilog problems / Sequential Design

What you must build

Synchronize a Gray-coded write pointer into the read domain and compare it against the local read pointer to generate a reliable empty flag — the core of every async FIFO.

Engineers use “Async-FIFO Empty Flag Synchronizer” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  [3:0] wptr_gray_in,
  input  [3:0] rptr_gray,
  output reg empty
);

  // Your code here — 2-flop sync wptr_gray_in, then empty = (synced value == rptr_gray).

endmodule

Why this shows up in interviews

Async-FIFO Empty Flag Synchronizer sits under Sequential Design (sequential, cdc, protocol). Concept: An async FIFO's write pointer lives in the write clock domain but the empty flag is needed in the read domain, so the pointer must cross safely — Gray coding ensures only one bit ever changes per increment, so even a partially-synchronized value during a transition is never wildly wrong. Double-flop the incoming Gray pointer ( meta , then wptr_gray_sync ), then compare it against the local read pointer: empty <= (wptr_gray_sync == rptr_gray) . Comparing the raw unsynchronized pointer directly against the local one skips the synchronizer chain entirely, reintroducing metastability risk into the empty flag.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ