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Part of Curriculum: Memory and FIFO Design (Module 4: Pointer MSB Wraparound & Full/Empty Detection)
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Level 3 Hard ★ Flagship #26 50 pts ✓ Solved

FIFO Full and Empty Detection — Pointer Logic

Queues & Buffers · memory, fifo, protocols, apb, uart, hard, fifo-pointers

Generate full and empty flags for an 8-entry circular FIFO using 4-bit pointers (3-bit address + 1 MSB wrap bit) without an occupancy counter.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
wr_ptr[3:0]rd_ptr[3:0]fullemptyFIFO FULL AND EMPTY DIGITAL HARDWARE BLOCK
⚡ Timing & Synthesizability Constraints

Timing Contract: Combinational flag evaluation from pointers.

RTL Constraints: FIFO depth = 8 ($2^3$). Pointers are 4-bit vectors `[3:0]`.

Objective: Understand the classic extra-MSB pointer technique to differentiate Full from Empty when wr_ptr == rd_ptr.

Prerequisites: FIFO architecture, circular buffer pointers, binary wrap bits.
Port Contract
NameDirWidthDescription
wr_ptrinput44-bit write pointer with MSB wrap bit
rd_ptrinput44-bit read pointer with MSB wrap bit
fulloutput1Full flag (identical address, inverted MSB)
emptyoutput1Empty flag (identical address and MSB)
Expected Waveform (Golden Timing Contract)
💡 Need Guidance? Progressive Hints (3 Levels)
Hint 1: Conceptual Direction & Hardware Primitives
When `wr_ptr == rd_ptr`, the queue is empty.
Hint 2: Implementation Architecture & Approach
When `wr_ptr` has written 8 more entries than `rd_ptr`, it points to the same memory slot (`wr_ptr[2:0] == rd_ptr[2:0]`), but its MSB wrap bit has toggled (`wr_ptr[3] != rd_ptr[3]`).
Hint 3: Edge Cases, Timing & Verilog Syntax
This classic technique avoids needing an extra adder/subtractor occupancy counter.
🔒 Reveal Verified Reference RTL Solution (Click to expand)
⚠️ Self-Discovery Warning: Try solving and simulating first! Viewing the verified reference implementation will bypass the real debugging experience.
Verified Synthesizable RTL 
module top_module(
  input  [3:0] wr_ptr,
  input  [3:0] rd_ptr,
  output       full,
  output       empty
);
  // Empty: all 4 bits match
  assign empty = (wr_ptr == rd_ptr);

  // Full: LSBs match (same memory slot) but MSBs differ (wr_ptr has wrapped around once more)
  assign full  = (wr_ptr[2:0] == rd_ptr[2:0]) && (wr_ptr[3] != rd_ptr[3]);
endmodule
Verilog-2001 / SV Saved
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Simulation Timing Diagram (VCD Waveform)
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RTL Problems / Level 3 · Queues & Buffers

What You Will Learn

By solving FIFO Full and Empty Detection — Pointer Logic, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Generate full and empty flags for an 8-entry circular FIFO using 4-bit pointers (3-bit address + 1 MSB wrap bit) without an occupancy counter.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Understand the classic extra-MSB pointer technique to differentiate Full from Empty when wr_ptr == rd_ptr.

Prerequisites: FIFO architecture, circular buffer pointers, binary wrap bits.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

NameDirWidthDescription
wr_ptrinput44-bit write pointer with MSB wrap bit
rd_ptrinput44-bit read pointer with MSB wrap bit
fulloutput1Full flag (identical address, inverted MSB)
emptyoutput1Empty flag (identical address and MSB)

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Combinational flag evaluation from pointers.

Synthesis Constraints: FIFO depth = 8 ($2^3$). Pointers are 4-bit vectors `[3:0]`.

Architectural Deep Dive & Implementation Walkthrough

If a buffer has depth $N = 2^k$, a $k$-bit pointer would cause Full and Empty to look identical ($wr == rd$). By sizing pointers to $k+1$ bits, the MSB acts as an epoch/wrap indicator. Empty occurs when both pointers are completely identical. Full occurs when the lower $k$ address bits match but the MSBs differ, proving the write pointer has wrapped around the circular buffer exactly one cycle ahead of the read pointer.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

['Checking `wr_ptr - rd_ptr == 8` using subtraction without properly sizing operands.', 'Applying binary pointer comparison across clock domains without Gray coding (in asynchronous FIFOs).']

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

This MSB-wrap method is the foundational algorithm required for Asynchronous FIFO design, because Gray-coded pointers can be compared across clock domains without arithmetic counters.

Starter RTL Code

module top_module(
  input  [3:0] wr_ptr,
  input  [3:0] rd_ptr,
  output       full,
  output       empty
);

  // Compute full and empty from pointers

endmodule

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution
module top_module(
  input  [3:0] wr_ptr,
  input  [3:0] rd_ptr,
  output       full,
  output       empty
);
  // Empty: all 4 bits match
  assign empty = (wr_ptr == rd_ptr);

  // Full: LSBs match (same memory slot) but MSBs differ (wr_ptr has wrapped around once more)
  assign full  = (wr_ptr[2:0] == rd_ptr[2:0]) && (wr_ptr[3] != rd_ptr[3]);
endmodule

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Frequently Asked Questions

What does FIFO Full and Empty Detection — Pointer Logic require?

Generate full and empty flags for an 8-entry circular FIFO using 4-bit pointers (3-bit address + 1 MSB wrap bit) without an occupancy counter. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: memory, fifo, protocols, apb, uart, hard, fifo-pointers. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of FIFO Full and Empty Detection — Pointer Logic to assess real-world synthesizability and race-condition awareness.