Async-FIFO Full Flag Synchronizer

Verilog problems / Sequential Design

What you must build

Synchronize a Gray-coded read pointer into the write domain and compare it against the local write pointer to detect full — including the extra wrap-bit check the empty flag never needs.

Engineers use “Async-FIFO Full Flag Synchronizer” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  [3:0] rptr_gray_in,
  input  [3:0] wptr_gray,
  output reg full
);

  // Your code here — 2-flop sync rptr_gray_in, then full = (top 2 bits inverted, bottom 2 bits equal) vs wptr_gray.

endmodule

Why this shows up in interviews

Async-FIFO Full Flag Synchronizer sits under Sequential Design (sequential, cdc, protocol). Concept: The full flag mirrors the empty flag's synchronizer structure — double-flop the incoming Gray read pointer, then compare — but the comparison itself is different: full means the write pointer has wrapped exactly one lap ahead of the read pointer, which in Gray code shows up as the two MSBs inverted while the low bits match: (wptr[3]!=rsync[3]) && (wptr[2]!=rsync[2]) && (wptr[1:0]==rsync[1:0]) . Reusing the empty flag's plain equality check here would report full only when the pointers are exactly equal — which is what empty looks like, not full.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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