3-Tap FIR Filter

Verilog problems / Sequential Design

What you must build

Implement a fixed-coefficient 3-tap FIR filter (1,2,1) over a signed input stream — the multiply-accumulate structure behind every digital smoothing/anti-aliasing filter.

Engineers use “3-Tap FIR Filter” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  signed [7:0] x_in,
  output reg signed [10:0] y_out
);

  // Your code here — keep x[n-1], x[n-2] in shift registers; y_out <= x_in + 2*x1 + x2.

endmodule

Why this shows up in interviews

3-Tap FIR Filter sits under Sequential Design (sequential, datapath). Concept: A 3-tap FIR filter computes a weighted sum of the current and two previous samples: y[n] = 1&middot;x[n] + 2&middot;x[n-1] + 1&middot;x[n-2] . Keep the last two samples in shift registers ( x1 , x2 ), multiply the center tap by 2 with a cheap left-shift ( x1<<<1 ), and register the sum. Dropping the center tap's weight ( x_in+x1+x2 instead of x_in+2*x1+x2 ) silently turns a binomial-weighted smoothing filter into a plain 3-sample average — same shape of circuit, different frequency response entirely.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

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• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
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