RTL Problems / Level 7 · Advanced RTL & Protocol Design
What You Will Learn
By solving Glitch-Free Clock Multiplexer with Handshake Feedback, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Design an industry-standard glitch-free clock switching controller that prevents runt pulses when dynamically alternating between asynchronous clock sources.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Clock gating, dynamic frequency scaling (DFS), negative-edge synchronizers, runt pulse hazards, CDC.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Port | Dir | Width | Description |
|---|---|---|---|
clk_0, clk_1 | input | 1, 1 | Independent, asynchronous clock inputs |
rst_n | input | 1 | Global asynchronous active-low reset |
sel | input | 1 | Clock select signal (0 = clk_0, 1 = clk_1) |
out_clk | output | 1 | Glitch-free multiplexed output clock |
active_clock | output | 1 | Status flag indicating currently driving clock |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Driven by asynchronous clock sources clk_0 and clk_1 with active-low async rst_n. Enables must toggle ONLY during clock low phases.
Synthesis Constraints: Strictly zero runt pulses on out_clk. No glitches during select transitions. Synthesizable Verilog-2001.
Architectural Deep Dive & Implementation Walkthrough
Why Pure Combinational Multiplexers Cause Clock Glitches
If you switch between two asynchronous clocks using a simple multiplexer (assign out_clk = sel ? clk_1 : clk_0;), switching when one clock is high and the other is low produces a momentary narrow pulse called a runt pulse.
Runt pulses violate setup and hold times of downstream flip-flops, causing chip-wide metastability and logic corruption.
The Glitch-Free Architecture Solution
- Negative-Edge Sampling: Enabling or disabling a clock signal only when the clock is low ensures that rising edges are never truncated.
- Cross-Feedback Handshaking: The target clock cannot turn on until the current clock has verified that its enable is 0.
- Metastability Hardening: Dual flip-flops in each clock domain absorb any metastability from asynchronous
selchanges.
Common RTL Designer Pitfalls
Triggering enable registers on posedge clk instead of negedge clk, which causes glitches during high phases.
Silicon & Hardware Engineering Notes
Standard cell libraries often provide specialized ICG (Integrated Clock Gating) cells with integrated negative-edge latches to save power and area.
Starter RTL Code
module top_module (
input wire clk_0,
input wire clk_1,
input wire rst_n,
input wire sel,
output wire out_clk,
output wire active_clock
);
// Implement glitch-free clock multiplexer:
// 1. Clock 0 enable logic clocked on negedge clk_0:
// Takes (~sel & ~en_clk1_stage2) and registers it through 2 negedge clk_0 flops.
// 2. Clock 1 enable logic clocked on negedge clk_1:
// Takes (sel & ~en_clk0_stage2) and registers it through 2 negedge clk_1 flops.
// 3. out_clk = (clk_0 & en_clk0) | (clk_1 & en_clk1).
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module (
input wire clk_0,
input wire clk_1,
input wire rst_n,
input wire sel,
output wire out_clk,
output wire active_clock
);
reg en_clk0_d1, en_clk0_d2;
reg en_clk1_d1, en_clk1_d2;
// Domain 0: Negative edge flops for clock 0 enable
always @(negedge clk_0 or negedge rst_n) begin
if (!rst_n) begin
en_clk0_d1 <= 1'b1;
en_clk0_d2 <= 1'b1;
end else begin
en_clk0_d1 <= (~sel) & (~en_clk1_d2);
en_clk0_d2 <= en_clk0_d1;
end
end
// Domain 1: Negative edge flops for clock 1 enable
always @(negedge clk_1 or negedge rst_n) begin
if (!rst_n) begin
en_clk1_d1 <= 1'b0;
en_clk1_d2 <= 1'b0;
end else begin
en_clk1_d1 <= sel & (~en_clk0_d2);
en_clk1_d2 <= en_clk1_d1;
end
end
// Glitch-free clock gating and OR recombination
assign out_clk = (clk_0 & en_clk0_d2) | (clk_1 & en_clk1_d2);
assign active_clock = en_clk1_d2;
endmodule
Related RTL Problems in Level 7
- Async-Assert / Sync-Deassert Reset — Assert reset the instant it goes active, but only release it once it has been clean for 2 clock edges — the standard reset architecture for any real design.
- 3-Flop CDC Synchronizer — A deeper 3-stage synchronizer for signals that need extra MTBF margin beyond the standard 2-flop chain.
- Synchronized Rising-Edge Detector — Safely synchronize an asynchronous level signal, then produce a clean single-cycle pulse the moment it rises in the local clock domain.
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Frequently Asked Questions
What does Glitch-Free Clock Multiplexer with Handshake Feedback require?
Design an industry-standard glitch-free clock switching controller that prevents runt pulses when dynamically alternating between asynchronous clock sources. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: advanced-rtl, soc-controllers, systemverilog, asic, fpga. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Glitch-Free Clock Multiplexer with Handshake Feedback to assess real-world synthesizability and race-condition awareness.