CDC Handshake Acknowledge Responder

Verilog problems / Sequential Design

What you must build

Synchronize an asynchronous request line and fire exactly one acknowledge pulse per request — never re-acking while the request is still held, only re-arming once it drops.

Engineers use “CDC Handshake Acknowledge Responder” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  req,
  output reg ack
);

  // Your code here — 2-flop sync req, then a 3rd stage to edge-detect and pulse ack once per request.

endmodule

Why this shows up in interviews

CDC Handshake Acknowledge Responder sits under Sequential Design (sequential, cdc, protocol). Concept: A 4-phase handshake responder synchronizes req with the usual 2-flop chain, then edge-detects the synchronized request to fire a single ack pulse: ack <= sync_req & ~req_prev . The extra req_prev register (a 3rd stage beyond the 2-flop sync) is what prevents re-acking every cycle the request stays high — without it, ack would just mirror the level and fire continuously for as long as req is asserted.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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