Low-Power Sleep/Wake FSM

Verilog problems / Sequential Design

What you must build

Enter a low-power sleep state on request and wake on an interrupt — but never actually go to sleep if a wake interrupt is already pending the instant sleep is requested.

Engineers use “Low-Power Sleep/Wake FSM” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  sleep_req,
  input  wake_irq,
  output reg sleeping,
  output reg wake_pulse
);

  // Your code here — AWAKE: if(sleep_req && !wake_irq) go to SLEEP. SLEEP: if(wake_irq) go to AWAKE, pulse wake_pulse.

endmodule

Why this shows up in interviews

Low-Power Sleep/Wake FSM sits under Sequential Design (sequential, fsm, low-power). Concept: A real race condition in power management: if sleep_req and wake_irq arrive on the exact same cycle, sleeping anyway would mean the wake event that just occurred is silently swallowed, leaving the system asleep waiting for a second wake interrupt that may never come: if(sleep_req && !wake_irq) ... . Dropping the !wake_irq guard means the FSM commits to sleep purely based on the request, without checking whether a wake is simultaneously being asserted — exactly the missed-wakeup race that guard exists to close.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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