Multi-Bit Bus Handshake Clock-Domain Crossing (CDC)

RTL Problems / Level 7 · Advanced RTL & Protocol Design

What You Will Learn

By solving Multi-Bit Bus Handshake Clock-Domain Crossing (CDC), you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a 4-phase REQ/ACK handshake synchronizer ensuring coherent multi-bit data bus transfer between asynchronous clock domains.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        src_clk,
  input  wire        src_rst_n,
  input  wire        src_valid,
  input  wire [15:0] src_data,
  output reg         src_ready,
  input  wire        dst_clk,
  input  wire        dst_rst_n,
  output reg         dst_valid,
  output reg  [15:0] dst_data
);

  // Implement 4-phase multi-bit handshake CDC:
  // 1. Source registers src_data into holding register and asserts src_req = 1.
  // 2. Cross src_req into dst_clk domain via 2-flop synchronizer -> dst_req_sync.
  // 3. When dst_req_sync = 1, capture holding register into dst_data, pulse dst_valid, assert dst_ack = 1.
  // 4. Cross dst_ack into src_clk domain via 2-flop synchronizer -> src_ack_sync.
  // 5. When src_ack_sync = 1, lower src_req = 0.

Verified Reference Solution

module top_module (
  input  wire        src_clk,
  input  wire        src_rst_n,
  input  wire        src_valid,
  input  wire [15:0] src_data,
  output reg         src_ready,
  input  wire        dst_clk,
  input  wire        dst_rst_n,
  output reg         dst_valid,
  output reg  [15:0] dst_data
);

  // Source domain state
  reg [15:0] data_hold;
  reg        src_req;

  // Synchronize src_req to dst_clk
  reg req_s1, req_s2;

  // Destination domain state
  reg dst_ack;
  reg req_s2_d;

  // Synchronize dst_ack to src_clk
  reg ack_s1, ack_s2;

  // Source domain logic
  always @(posedge src_clk or negedge src_rst_n) begin
    if (!src_rst_n) begin
      src_ready <= 1'b1;
      src_req   <= 1'b0;
      data_hold <= 16'h0;
      ack_s1    <= 1'b0;
      ack_s2    <= 1'b0;
    end else begin
      ack_s1 <= dst_ack;
      ack_s2 <= ack_s1;

      if (src_ready && src_valid) begin
        src_ready <= 1'b0;
        src_req   <= 1'b1;
        data_hold <= src_data;
      end else if (src_req && ack_s2) begin
        src_req <= 1'b0;
      end else if (!src_req && !ack_s2 && !src_ready) begin
        src_ready <= 1'b1; // Completed 4-phase handshake
      end
    end
  end

  // Destination domain logic
  always @(posedge dst_clk or negedge dst_rst_n) begin
    if (!dst_rst_n) begin
      req_s1    <= 1'b0;
      req_s2    <= 1'b0;
      req_s2_d  <= 1'b0;
      dst_ack   <= 1'b0;
      dst_valid <= 1'b0;
      dst_data  <= 16'h0;
    end else begin
      req_s1    <= src_req;
      req_s2    <= req_s1;
      req_s2_d  <= req_s2;
      dst_valid <= 1'b0;

      if (req_s2 && !req_s2_d) begin
        // Rising edge of request in destination domain
        dst_data  <= data_hold;
        dst_valid <= 1'b1;
        dst_ack   <= 1'b1;
      end else if (!req_s2 && dst_ack) begin
        dst_ack <= 1'b0;
      end
    end
  end

endmodule

Related RTL Problems in Level 7

• Async-Assert / Sync-Deassert Reset — Assert reset the instant it goes active, but only release it once it has been clean for 2 clock edges — the standard reset architecture for any real design.
• 3-Flop CDC Synchronizer — A deeper 3-stage synchronizer for signals that need extra MTBF margin beyond the standard 2-flop chain.
• Synchronized Rising-Edge Detector — Safely synchronize an asynchronous level signal, then produce a clean single-cycle pulse the moment it rises in the local clock domain.

Frequently Asked Questions