Parameterized Register Slice — Pipeline and Backpressure

RTL Problems / Level 3 · On-Chip Protocols

What You Will Learn

By solving Parameterized Register Slice — Pipeline and Backpressure, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a Parameterized Register Slice (Skid Buffer) of width DATA_WIDTH (default 8) that breaks combinational paths in BOTH forward and backward directions with 0 bubble cycles.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module #(
  parameter DATA_WIDTH = 8
)(
  input                    clk,
  input                    areset_n,
  input                    s_valid,
  output reg               s_ready,
  input   [DATA_WIDTH-1:0] s_data,
  output reg               m_valid,
  input                    m_ready,
  output reg [DATA_WIDTH-1:0] m_data
);

  // Full Skid Buffer breaking both forward and backward timing paths

endmodule

Verified Reference Solution

module top_module #(
  parameter DATA_WIDTH = 8
)(
  input                    clk,
  input                    areset_n,
  input                    s_valid,
  output reg               s_ready,
  input   [DATA_WIDTH-1:0] s_data,
  output reg               m_valid,
  input                    m_ready,
  output reg [DATA_WIDTH-1:0] m_data
);
  reg [DATA_WIDTH-1:0] skid_data;
  reg                  skid_valid;

  always @(posedge clk or negedge areset_n) begin
    if (!areset_n) begin
      s_ready    <= 1'b1;
      m_valid    <= 1'b0;
      m_data     <= {DATA_WIDTH{1'b0}};
      skid_valid <= 1'b0;
      skid_data  <= {DATA_WIDTH{1'b0}};
    end else begin
      if (m_ready) begin
        if (skid_valid) begin
          m_valid    <= 1'b1;
          m_data     <= skid_data;
          skid_valid <= 1'b0;
          s_ready    <= 1'b1;
        end else if (s_valid && s_ready) begin
          m_valid    <= 1'b1;
          m_data     <= s_data;
          s_ready    <= 1'b1;
        end else begin
          m_valid    <= 1'b0;
          s_ready    <= 1'b1;
        end
      end else begin // m_ready is low (downstream stalled)
        if (s_valid && s_ready) begin
          skid_data  <= s_data;
          skid_valid <= 1'b1;
          s_ready    <= 1'b0; // can no longer accept when skid is full
        end
      end
    end
  end
endmodule

Related RTL Problems in Level 3

• Synchronous RAM — Memory Read/Write — Design a 16-word by 8-bit synchronous RAM (16x8) with synchronous write and synchronous read.
• Single-Port RAM with Write Enable — Memory Control — Implement a 32-word x 8-bit single-port synchronous RAM with read-first (read-during-write) behavior.
• Synchronous FIFO — FIFO Architecture — Design an 8-entry by 8-bit synchronous First-In First-Out (FIFO) buffer with write enable (wr_en), read enable (rd_en), full, and empty flags.

Frequently Asked Questions