Power-On Reset (POR) Generator

Verilog problems / Sequential Design

What you must build

Hold every flop in reset for a fixed number of cycles after power-up before releasing them — the counter-based POR sitting between a raw power rail and the rest of a chip.

Engineers use “Power-On Reset (POR) Generator” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  trigger,
  output reg reset_out
);

  // Your code here — on trigger, hold reset_out=1 for exactly 8 cycles (counting 0..7), then release.

endmodule

Why this shows up in interviews

Power-On Reset (POR) Generator sits under Sequential Design (sequential, reset, counter). Concept: A POR simply counts cycles while reset is held, and releases exactly when the count reaches its target: if(cnt==7) reset_out<=0; else cnt<=cnt+1; , giving 8 total held cycles (cnt running 0 through 7 inclusive). Comparing against one less than the intended count ( cnt==6 instead of cnt==7 ) releases reset a full cycle early — a classic off-by-one in a hold-for-N-cycles counter that's easy to get wrong in either direction depending on whether the count starts at 0 or 1.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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