Power Rail Sequencer

Verilog problems / Sequential Design

What you must build

Bring up 3 power rails one at a time in a fixed order — and bring them down in the exact reverse order, since powering down the rail others depend on first can damage real silicon.

Engineers use “Power Rail Sequencer” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  power_up,
  input  power_down,
  output reg [2:0] rail_en
);

  // Your code here — power_up: turn on rails in order 0,1,2 (one per cycle, lowest unset bit first).
  // power_down: turn off rails in REVERSE order 2,1,0 (one per cycle, highest set bit first).

endmodule

Why this shows up in interviews

Power Rail Sequencer sits under Sequential Design (sequential, fsm, power). Concept: Power sequencing during boot and shutdown is order-critical: rails come up 0→1→2, but must come down 2→1→0 — the reverse — because later rails typically depend on earlier ones staying powered while they're active. The bug is deceptively small: powering down in the same order as power-up (checking rail_en[0] first instead of rail_en[2] ) turns off the foundational rail while the ones that depend on it are still active — on real hardware, exactly the kind of sequencing mistake that can damage a board, not just misbehave in simulation.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ