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Part of Curriculum: CDC, RDC and Low-Power RTL (Module 2: Pulse Synchronizers (Fast-to-Slow & Slow-to-Fast))
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Level 7 Expert ★ Advanced #58 50 pts ✓ Solved

Toggle-Based Pulse Synchronizer Across Asynchronous Clock Domains

Advanced RTL & Protocol Design · advanced-rtl, cdc-and-rdc, systemverilog, asic, fpga

Design a toggle-based pulse synchronizer capable of reliably transferring 1-cycle event pulses between fast-to-slow and slow-to-fast clock domains.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
SRC REGDOMAIN ASYNC 1METASTABLESYNC 2RESOLVEDDOMAIN A (clk_src)DOMAIN B (clk_dst)src_pulsedst_pulse
⚡ Timing & Synthesizability Constraints

Timing Contract: Completely asynchronous src_clk and dst_clk. Ensure consecutive pulses in src_clk are separated by at least 3 dst_clk periods to prevent pulse collisions.

RTL Constraints: No missed pulses. Synthesizable Verilog-2001.

Objective: Implement a pulse synchronizer. Directly synchronizing a 1-cycle pulse from a fast clock domain into a slower clock domain often fails because the pulse can vanish between slow clock edges. Use a toggle register in the source domain, cross the level signal through a 2-flop synchronizer in the destination domain, and use an edge detector (XOR) to generate an exact 1-cycle pulse in the destination domain.

Prerequisites: Pulse swallowing problem in fast-to-slow CDC, toggle flip-flops, 2-flop synchronizers, edge detection.
Port Contract
PortDirWidthDescription
src_clk, src_rst_ninput1Source clock domain and reset
src_pulseinput11-cycle event pulse to be transmitted
dst_clk, dst_rst_ninput1Destination clock domain and reset
dst_pulseoutput1Clean 1-cycle pulse reproduced in destination domain
Expected Waveform (Golden Timing Contract)
💡 Need Guidance? Progressive Hints (3 Levels)
Hint 1: Conceptual Direction & Hardware Primitives
A 1-cycle pulse in a fast domain can easily be swallowed if sampled directly by a slower clock.
Hint 2: Implementation Architecture & Approach
Convert the pulse to a toggle: src_toggle <= ~src_toggle on every src_pulse.
Hint 3: Edge Cases, Timing & Verilog Syntax
Synchronize src_toggle into dst_clk using 2 flip-flops. Then an XOR between the 2nd and 3rd flip-flop outputs a clean 1-cycle pulse on every transition.
🔒 Reveal Verified Reference RTL Solution (Click to expand)
⚠️ Self-Discovery Warning: Try solving and simulating first! Viewing the verified reference implementation will bypass the real debugging experience.
Verified Synthesizable RTL 
module top_module (
  input  wire src_clk,
  input  wire src_rst_n,
  input  wire src_pulse,
  input  wire dst_clk,
  input  wire dst_rst_n,
  output reg  dst_pulse
);

  reg src_toggle;
  reg dst_s1, dst_s2, dst_s3;

  // Source domain: Pulse-to-Toggle
  always @(posedge src_clk or negedge src_rst_n) begin
    if (!src_rst_n) begin
      src_toggle <= 1'b0;
    end else if (src_pulse) begin
      src_toggle <= ~src_toggle;
    end
  end

  // Destination domain: 2-Flop Sync + 3rd Flop for Edge Detection
  always @(posedge dst_clk or negedge dst_rst_n) begin
    if (!dst_rst_n) begin
      dst_s1    <= 1'b0;
      dst_s2    <= 1'b0;
      dst_s3    <= 1'b0;
      dst_pulse <= 1'b0;
    end else begin
      dst_s1    <= src_toggle;
      dst_s2    <= dst_s1;
      dst_s3    <= dst_s2;
      dst_pulse <= dst_s2 ^ dst_s3; // Pulses on ANY transition (0->1 or 1->0)
    end
  end

endmodule
Verilog-2001 / SV Saved
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RTL Problems / Level 7 · Advanced RTL & Protocol Design

What You Will Learn

By solving Toggle-Based Pulse Synchronizer Across Asynchronous Clock Domains, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a toggle-based pulse synchronizer capable of reliably transferring 1-cycle event pulses between fast-to-slow and slow-to-fast clock domains.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Implement a pulse synchronizer. Directly synchronizing a 1-cycle pulse from a fast clock domain into a slower clock domain often fails because the pulse can vanish between slow clock edges. Use a toggle register in the source domain, cross the level signal through a 2-flop synchronizer in the destination domain, and use an edge detector (XOR) to generate an exact 1-cycle pulse in the destination domain.

Prerequisites: Pulse swallowing problem in fast-to-slow CDC, toggle flip-flops, 2-flop synchronizers, edge detection.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

PortDirWidthDescription
src_clk, src_rst_ninput1Source clock domain and reset
src_pulseinput11-cycle event pulse to be transmitted
dst_clk, dst_rst_ninput1Destination clock domain and reset
dst_pulseoutput1Clean 1-cycle pulse reproduced in destination domain

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Completely asynchronous src_clk and dst_clk. Ensure consecutive pulses in src_clk are separated by at least 3 dst_clk periods to prevent pulse collisions.

Synthesis Constraints: No missed pulses. Synthesizable Verilog-2001.

Architectural Deep Dive & Implementation Walkthrough

The Pulse Swallowing Problem in CDC

When sending a 1-clock-cycle pulse from a fast clock domain (e.g. 500 MHz, 2 ns width) to a slow clock domain (e.g. 50 MHz, 20 ns period), the pulse frequently asserts and deasserts entirely between two rising edges of the slow clock. A direct 2-flop synchronizer will miss the pulse completely.

Toggle-Based Pulse Synchronization

  1. Pulse to Toggle: In the source domain, a T-type flip-flop toggles its state ($0 o 1$ or $1 o 0$) whenever src_pulse = 1 occurs. This transforms a transient pulse into a permanent DC level change.
  2. Level Synchronization: The toggle level crosses into the destination domain via a standard 2-flop synchronizer.
  3. Edge Detection: In the destination domain, a third register stores the delayed state. An XOR between the 2nd and 3rd flops detects any state transition, generating a clean 1-cycle pulse in the destination clock domain.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

Using a simple rising-edge detector (in & ~in_d) instead of an XOR. Since the source toggles both 0->1 and 1->0, an XOR is required to detect every pulse.

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

Consecutive source pulses must be separated by at least 2.5 destination clock periods to allow the toggle transition to propagate through the synchronizer chain.

Starter RTL Code

module top_module (
  input  wire src_clk,
  input  wire src_rst_n,
  input  wire src_pulse,
  input  wire dst_clk,
  input  wire dst_rst_n,
  output reg  dst_pulse
);

  // Implement Toggle-Based Pulse Synchronizer:
  // 1. In src_clk: toggle a register whenever src_pulse is high.
  // 2. Synchronize toggle register into dst_clk through 2 flip-flops.
  // 3. In dst_clk: detect any level change (using an XOR with a delayed flop) to generate 1-cycle dst_pulse.

endmodule

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution
module top_module (
  input  wire src_clk,
  input  wire src_rst_n,
  input  wire src_pulse,
  input  wire dst_clk,
  input  wire dst_rst_n,
  output reg  dst_pulse
);

  reg src_toggle;
  reg dst_s1, dst_s2, dst_s3;

  // Source domain: Pulse-to-Toggle
  always @(posedge src_clk or negedge src_rst_n) begin
    if (!src_rst_n) begin
      src_toggle <= 1'b0;
    end else if (src_pulse) begin
      src_toggle <= ~src_toggle;
    end
  end

  // Destination domain: 2-Flop Sync + 3rd Flop for Edge Detection
  always @(posedge dst_clk or negedge dst_rst_n) begin
    if (!dst_rst_n) begin
      dst_s1    <= 1'b0;
      dst_s2    <= 1'b0;
      dst_s3    <= 1'b0;
      dst_pulse <= 1'b0;
    end else begin
      dst_s1    <= src_toggle;
      dst_s2    <= dst_s1;
      dst_s3    <= dst_s2;
      dst_pulse <= dst_s2 ^ dst_s3; // Pulses on ANY transition (0->1 or 1->0)
    end
  end

endmodule

Related RTL Problems in Level 7

  • Async-Assert / Sync-Deassert Reset — Assert reset the instant it goes active, but only release it once it has been clean for 2 clock edges — the standard reset architecture for any real design.
  • 3-Flop CDC Synchronizer — A deeper 3-stage synchronizer for signals that need extra MTBF margin beyond the standard 2-flop chain.
  • Synchronized Rising-Edge Detector — Safely synchronize an asynchronous level signal, then produce a clean single-cycle pulse the moment it rises in the local clock domain.

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Frequently Asked Questions

What does Toggle-Based Pulse Synchronizer Across Asynchronous Clock Domains require?

Design a toggle-based pulse synchronizer capable of reliably transferring 1-cycle event pulses between fast-to-slow and slow-to-fast clock domains. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: advanced-rtl, cdc-and-rdc, systemverilog, asic, fpga. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Toggle-Based Pulse Synchronizer Across Asynchronous Clock Domains to assess real-world synthesizability and race-condition awareness.