Stretch-and-Synchronize Pulse

Verilog problems / Sequential Design

What you must build

Widen a fast, possibly very short pulse to guarantee it's caught by a much slower destination clock, then synchronize the stretched level cleanly across domains.

Engineers use “Stretch-and-Synchronize Pulse” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  fast_pulse,
  output reg sync_pulse
);

  // Your code here — stretch fast_pulse with a small counter, then 2-flop sync + edge-detect the stretched level.

endmodule

Why this shows up in interviews

Stretch-and-Synchronize Pulse sits under Sequential Design (sequential, cdc). Concept: If the source pulse can be shorter than one destination clock period, a synchronizer might sample right between edges and miss it entirely. Stretching fixes this: latch a small counter on fast_pulse and hold an internal stretched flag high until it expires, guaranteeing at least a few destination-clock cycles of visibility. Only then does the usual 2-flop-sync-plus-edge-detect pipeline turn it back into a single clean pulse. Skipping the stretch stage (synchronizing fast_pulse directly) works fine in simulation but is exactly the kind of shortcut that misses real pulses on real silicon.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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