Scan Chain Shift Register

Verilog problems / Sequential Design

What you must build

A 4-flop scan chain that captures functional data in normal operation but shifts a test pattern straight through when scan mode is enabled — the DFT structure behind every ATPG test on real silicon.

Engineers use “Scan Chain Shift Register” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  scan_enable,
  input  scan_in,
  input  [3:0] func_d,
  output [3:0] q
);

  // Your code here — scan_enable: shift {ff[2:0],scan_in} through the chain. Else: capture func_d.

endmodule

Why this shows up in interviews

Scan Chain Shift Register sits under Sequential Design (sequential, dft). Concept: Scan mode must genuinely shift the chain — each flop takes on the previous flop's value, carrying every bit one position along: ff <= {ff[2:0], scan_in} . A version that only writes the new scan-in bit into the bottom position while zeroing everything else ( ff <= {3'b000, scan_in} ) isn't a chain at all — it clobbers the 3 bits that were supposed to shift along instead of preserving and moving them, so scanning a test pattern through destroys the chain's contents instead of propagating them.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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