Streaming Frame Parity Checker

Verilog problems / Sequential Design

What you must build

Accumulate the running parity of a serial bit stream one bit per clock, resetting cleanly at the start of every 8-bit frame.

Engineers use “Streaming Frame Parity Checker” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input      clk,
  input      rst,
  input      bit_in,
  output reg parity_out,
  output reg frame_done
);

  // Your code here — 3-bit position counter; reset the accumulator at the start of each frame.

endmodule

Why this shows up in interviews

Streaming Frame Parity Checker sits under Sequential Design (sequential, parity). Concept: A 3-bit counter tracks position within the frame. The first bit of a new frame ( cnt==0 ) loads the accumulator directly; every other bit XORs in. frame_done must be a registered flag driven by the counter's value from the previous cycle — computing it straight off the live counter fires one cycle too early, before the frame's last bit has even been captured.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ