Shift-Add Multiplier

Verilog problems / Sequential Design

What you must build

Multiply two unsigned 4-bit numbers using the classic shift-add algorithm — one bit of the multiplier examined per cycle, exactly how early CPUs implemented multiplication in hardware before dedicated multiplier arrays.

Engineers use “Shift-Add Multiplier” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  start,
  input  [3:0] a,
  input  [3:0] b,
  output reg [7:0] product,
  output reg done
);

  // Your code here — 4 iterations: if multiplier LSB is 1, add multiplicand into product; then shift multiplicand left, multiplier right.

Why this shows up in interviews

Shift-Add Multiplier sits under Sequential Design (sequential, datapath). Concept: Shift-add multiplication processes the multiplier one bit at a time: if the current LSB of the multiplier is 1, add the (progressively left-shifted) multiplicand into an accumulating product; either way, shift the multiplicand left and the multiplier right, and repeat for every bit. Forgetting to shift the multiplier means the same LSB is examined every cycle instead of advancing through the bits — the multiplicand still grows correctly, but the decision of when to add it is stuck testing the same (increasingly stale) bit forever.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ