Valid-Ready Handshake — Flow Control — RTL Design Practice & FSM Timing

Implement a forward-registered valid-ready handshake pipeline stage with backpressure handling (data transfers only when valid && ready).

RTL Problems / Level 3 · On-Chip Protocols

What You Will Learn

By solving Valid-Ready Handshake — Flow Control, you will acquire core industry skills:

Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Implement a forward-registered valid-ready handshake pipeline stage with backpressure handling (data transfers only when valid && ready).

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Understand AXI-style valid/ready flow control, handshake rules, backpressure propagation, and preventing data loss.

Prerequisites: Synchronous registers, handshake protocol rules.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Name	Dir	Width	Description
`clk`	input	1	Clock signal
`areset_n`	input	1	Active-low reset
`s_valid`	input	1	Upstream valid
`s_ready`	output	1	Upstream ready
`s_data`	input	8	Upstream data
`m_valid`	output	1	Downstream valid
`m_ready`	input	1	Downstream ready
`m_data`	output	8	Downstream data

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Transfer commits precisely on `posedge clk` when `valid && ready`. Neither side can revoke data once valid is asserted.

Synthesis Constraints: Standard AXI rule: `valid` must NOT depend combinationally on `ready` (to prevent deadlocks).

Architectural Deep Dive & Implementation Walkthrough

The Valid-Ready protocol is the universal streaming interface used across AMBA AXI-Stream, PCIe TLP pipelines, and AI tensor accelerators. It enforces flow control without drops: data is safely held until the consumer confirms reception with `ready`.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

['Making `m_valid` depend combinationally on `m_ready`: this is strictly prohibited by the AXI specification and creates combinational feedback loops.', 'Overwriting `m_data` while `m_ready = 0`, corrupting unread data.']

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

A simple forward register breaks the timing path on `data` and `valid`, but leaves `s_ready` dependent combinationally on `m_ready`. To break timing in both directions, use a full 2-entry Skid Buffer.

Starter RTL Code

module top_module(
  input        clk,
  input        areset_n,
  input        s_valid,
  output       s_ready,
  input  [7:0] s_data,
  output reg   m_valid,
  input        m_ready,
  output reg [7:0] m_data
);

  // Valid-ready forward registered stage

endmodule

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution

module top_module(
  input        clk,
  input        areset_n,
  input        s_valid,
  output       s_ready,
  input  [7:0] s_data,
  output reg   m_valid,
  input        m_ready,
  output reg [7:0] m_data
);
  // Stage can accept data if empty (!m_valid) or if downstream is currently accepting (m_ready)
  assign s_ready = !m_valid || m_ready;

  always @(posedge clk or negedge areset_n) begin
    if (!areset_n) begin
      m_valid <= 1'b0;
      m_data  <= 8'd0;
    end else if (s_ready) begin
      m_valid <= s_valid;
      if (s_valid)
        m_data <= s_data;
    end
  end
endmodule

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Frequently Asked Questions

What does Valid-Ready Handshake — Flow Control require?

Implement a forward-registered valid-ready handshake pipeline stage with backpressure handling (data transfers only when valid && ready). Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: memory, fifo, protocols, apb, uart, hard, axi-/-streaming. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Valid-Ready Handshake — Flow Control to assess real-world synthesizability and race-condition awareness.