Voltage Margin Monitor

Verilog problems / Combinational Design

What you must build

Flag a fault when the supply voltage strays outside its safe band in either direction — over-voltage or under-voltage, either one is a problem.

Engineers use “Voltage Margin Monitor” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [7:0] vsense,
  output over_voltage,
  output under_voltage,
  output fault
);

  // Your code here — over_voltage=(vsense>200); under_voltage=(vsense<50); fault = over_voltage || under_voltage.

endmodule

Why this shows up in interviews

Voltage Margin Monitor sits under Combinational Design (combinational, monitor, power). Concept: The two individual threshold checks are independent conditions, and a fault should fire if either one is true: fault = over_voltage || under_voltage . Using && instead of || silently changes the meaning to "both over AND under voltage at the same time" — a condition that's logically impossible for a single sensed value, so the fault output would never assert at all, no matter how far out of range the voltage strays.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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