1. What is Routing?
After placement and CTS, every cell has a physical location and the clock network is built. Routing draws the metal wires (and vias between layers) that implement every logical connection in the netlist. The output is a geometrically correct layout ready for sign-off verification.
Input: Post-CTS DEF (placed cells + clock tree) + netlist (connections) + technology LEF (layer rules)
Output: Routed DEF/GDSII — every net has a wire path, zero DRC violations
Routing order: Clock nets (NDR/shielded) → Special nets (power/ground) → Signal nets
Output: Routed DEF/GDSII — every net has a wire path, zero DRC violations
Routing order: Clock nets (NDR/shielded) → Special nets (power/ground) → Signal nets
2. Global Routing vs Detailed Routing
Global Routing
Divides the chip into routing tiles (GRC — Global Routing Cells). Assigns each net to a sequence of tiles and metal layers without drawing exact geometries. Goal: ensure all nets can be routed (no overflow), establish layer assignments, and identify congestion before committing wire shapes.
Detailed Routing
Takes the global routing guide for each net and draws exact wire shapes — specifying X/Y coordinates, width, via types. Must satisfy every DRC rule in the process design kit (PDK). The output is GDSII-ready geometry. Uses track-assignment and search-and-repair algorithms.
| Aspect | Global Routing | Detailed Routing |
|---|---|---|
| Granularity | Tile-level (coarse) | Track-level (exact geometry) |
| DRC awareness | Approximate (capacity-based) | Full DRC enforcement |
| Output | Routing guides (layer + tile) | Wire shapes + via positions (GDSII) |
| Goal | Assign layers, find feasible routes | Draw legal wires, fix all DRC |
| Congestion | Detects overflow tiles | Resolves overflow by rip-and-reroute |
| Runtime | Fast (minutes) | Slow (hours for large designs) |
3. Design Rule Checks (DRC) in Routing
Design rules are foundry-specified geometric constraints on metal wires and vias. Violating them causes manufacturing defects. The router must satisfy all rules while routing.
4. Antenna Effect
During chip fabrication, plasma etching creates ionized particles. Long metal wires that are connected to a transistor gate (but not yet connected to the rest of the circuit in that fabrication stage) collect charge. If enough charge accumulates, it tunnels through the gate oxide — permanently damaging it.
Antenna Ratio = Wire Area / Gate Oxide Area < Foundry Limit (e.g., 400:1)
5. Crosstalk & Signal Integrity
As wires become thinner and more densely packed, capacitive coupling between adjacent wires becomes significant. A switching wire (aggressor) induces a voltage disturbance on a quiet wire (victim).
Two Types of Crosstalk
Crosstalk Noise (Glitch)
A static victim net receives a glitch voltage from the aggressor's switching. If the glitch exceeds 50% Vdd on a combinational net, it can propagate as a logic error. Most dangerous on high-impedance nodes (large fanout, weak driver).
Crosstalk Delay
A switching aggressor charges/discharges coupling capacitance in a way that speeds up or slows down the victim's own transition. Same-direction switching: victim speeds up (less delay). Opposite-direction switching: victim slows down (more delay → possible setup violation).
Crosstalk Fixes
| Fix | Mechanism | Trade-off |
|---|---|---|
| Increase wire spacing | Reduces coupling capacitance C_c ∝ 1/distance | Uses more routing resources |
| Add shielding wire | VSS/VDD wire between aggressor and victim absorbs coupling | Consumes a routing track |
| Swap metal layers | Route victim on a different layer (perpendicular routing reduces coupling) | May increase via count |
| Buffer insertion | Stronger driver on victim → lower impedance → less susceptible to noise | Adds power, area |
| Net reordering | Rearrange parallel wires so aggressor is between VSS shields | May increase wirelength |
| Shorter parallel run | Limit length where two nets run parallel (coupling ∝ parallel length) | May require longer detour |
Crosstalk = C_c / (C_total) where C_c is coupling capacitance and C_total is total capacitance on the victim net. The coupling ratio determines noise amplitude: ratio >0.3 is considered dangerous for critical nets.
6. Routing Quality Metrics
| Metric | Definition | Target |
|---|---|---|
| DRC violations | Number of design rule violations (short, spacing, width, etc.) | 0 (zero DRC at sign-off) |
| WNS (post-route) | Worst Negative Slack after routing with actual RC parasitics | WNS ≥ 0 (no setup violations) |
| TNS (post-route) | Total Negative Slack — sum of all setup violations | TNS = 0 |
| Hold violations | Paths where data arrives too fast relative to the clock | 0 hold violations |
| Antenna violations | Wires exceeding foundry antenna ratio limits | 0 (fixed before tapeout) |
| Routing completion | % of nets fully routed (no opens) | 100% |
| Via count | Total vias in the design | Minimize (vias = resistance + reliability risk) |
| Total wirelength | Sum of all metal wire lengths | Minimize (less wire = less delay + power) |
7. Routing Commands — Innovus & ICC2
| Tool | Command | Purpose |
|---|---|---|
| Innovus | route_design | Full routing: global + detailed |
| Innovus | route_design -global_detail | Global + detailed routing in one pass |
| Innovus | setNanoRouteMode -routeWithTimingDriven true | Enable timing-driven routing |
| Innovus | setNanoRouteMode -routeWithSiDriven true | Enable signal integrity-driven routing |
| Innovus | verify_drc | Run DRC check after routing |
| Innovus | verify_connectivity | Check for opens (missing connections) |
| Innovus | verifyAntennaRule | Check antenna violations |
| Innovus | report_timing -max_paths 50 -late | Post-route setup timing |
| Innovus | report_timing -max_paths 50 -early | Post-route hold timing |
| ICC2 | route_auto | Automatic global + detailed routing |
| ICC2 | route_opt | Post-route optimization (timing + DRC) |
| ICC2 | check_routes | DRC + connectivity check |
| OpenROAD | global_route | FastRoute global routing |
| OpenROAD | detailed_route | TritonRoute detailed routing |
Routing Best Practices
- Route clock nets first with NDR rules, then power/ground, then signal nets
- Enable timing-driven routing: router prioritizes critical paths for better slack
- Run incremental DRC fix between global and detailed routing — cheaper to fix early
- Check antenna violations immediately after routing — before post-route timing
- Use via optimization to minimize resistance (prefer fat vias, via pillars on critical nets)
- For 7nm and below: double patterning constraints add coloring rules — use MPL-aware router
- Post-route ECO (Engineering Change Order) is expensive — resolve timing during routing optimization
8. Interview Questions & Answers
What is the difference between global routing and detailed routing?
Global routing divides the chip into routing tiles (GRCs) and assigns each net to a sequence of tiles + metal layers. It doesn't draw exact wire shapes — just routing "guides." Goal: verify routability, identify congestion, establish layer assignments. Fast (minutes).
Detailed routing takes the global guides and draws exact wire geometries meeting all DRC rules: specific X/Y coordinates, widths, via sizes, and spacing. Handles all physical constraints from the PDK. Slow (hours). Output is GDSII-ready layout. Uses algorithms like maze routing (Lee algorithm), A*, or track-assignment + rip-and-reroute for DRC violations.
Detailed routing takes the global guides and draws exact wire geometries meeting all DRC rules: specific X/Y coordinates, widths, via sizes, and spacing. Handles all physical constraints from the PDK. Slow (hours). Output is GDSII-ready layout. Uses algorithms like maze routing (Lee algorithm), A*, or track-assignment + rip-and-reroute for DRC violations.
What is the antenna effect and how do you fix it?
During plasma etching in fabrication, long metal wires connected to gate inputs accumulate charge. If the wire-to-gate-area ratio (antenna ratio) exceeds the foundry limit (e.g., 400:1), the charge permanently damages the gate oxide.
Fix 1 — Antenna diode: Insert a reverse-biased diode (forward-biased in plasma) near the gate. During fabrication, the diode bleeds excess charge to VSS, protecting the gate oxide. Most common fix for small violations.
Fix 2 — Metal jumper: Break the long wire by jumping to a higher metal layer at some point, then returning. Since each metal layer's antenna accumulation is counted separately, the jump resets the count. Used when diode placement is constrained.
Fix 1 — Antenna diode: Insert a reverse-biased diode (forward-biased in plasma) near the gate. During fabrication, the diode bleeds excess charge to VSS, protecting the gate oxide. Most common fix for small violations.
Fix 2 — Metal jumper: Break the long wire by jumping to a higher metal layer at some point, then returning. Since each metal layer's antenna accumulation is counted separately, the jump resets the count. Used when diode placement is constrained.
What are the two types of crosstalk and how does each affect timing?
1. Crosstalk noise (glitch): A static victim net gets a voltage glitch from an adjacent switching aggressor net through coupling capacitance. If the glitch exceeds the logic threshold (~50% Vdd), it can propagate as a false logic transition. Worst on high-impedance nodes with weak drivers.
2. Crosstalk delay: A switching aggressor changes the effective capacitance seen by the victim during its own switching. Same-direction switch: victim speeds up (beneficial, but can cause hold violations). Opposite-direction switch: victim slows down (detrimental — causes setup violations). STA tools model both as "pessimistic delay" for sign-off.
Fix: Increase wire spacing, add VSS shielding, swap metal layers, insert buffers, reduce parallel run length.
2. Crosstalk delay: A switching aggressor changes the effective capacitance seen by the victim during its own switching. Same-direction switch: victim speeds up (beneficial, but can cause hold violations). Opposite-direction switch: victim slows down (detrimental — causes setup violations). STA tools model both as "pessimistic delay" for sign-off.
Fix: Increase wire spacing, add VSS shielding, swap metal layers, insert buffers, reduce parallel run length.
What are the most common DRC violations in routing and how are they fixed?
Short: Two wires on the same layer overlap — fix by rerouting one wire to a different layer or different track.
Spacing violation: Two same-layer wires too close — fix by rip-and-reroute with wider spacing or rerouting one wire via a detour.
Width violation: Wire narrower than min width — fix by widening or rerouting.
Via enclosure: Metal doesn't extend far enough past the via boundary — fix by extending metal stub or using a larger via type.
Open (missing connection): A net is not fully connected — search-and-repair finds alternative route.
EOL spacing: Wire end too close to adjacent wire — fix by shortening wire or adding more space.
Post-route DRC fix runs "search-and-repair" (S&R) in a loop: find violations → rip out local route → reroute with DRC awareness. Repeated until zero violations.
Spacing violation: Two same-layer wires too close — fix by rip-and-reroute with wider spacing or rerouting one wire via a detour.
Width violation: Wire narrower than min width — fix by widening or rerouting.
Via enclosure: Metal doesn't extend far enough past the via boundary — fix by extending metal stub or using a larger via type.
Open (missing connection): A net is not fully connected — search-and-repair finds alternative route.
EOL spacing: Wire end too close to adjacent wire — fix by shortening wire or adding more space.
Post-route DRC fix runs "search-and-repair" (S&R) in a loop: find violations → rip out local route → reroute with DRC awareness. Repeated until zero violations.
Why do signal wires route on lower layers while power and clock use top metal layers?
Top metal layers for power/clock: Top metals (M7–M9 in advanced nodes) are thicker and wider → lower sheet resistance per unit length → less IR drop on power rails → lower insertion delay on clock trunks. Also, top-layer wires span the full die with fewer vias (fewer resistance bottlenecks).
Lower layers for signals: M2–M5 carry local connections between nearby cells. Signal nets are typically short (few hundred µm) so the higher resistance of thinner lower-layer metal is acceptable. Also, signals don't need low-resistance routing — RC delay is budgeted in timing analysis.
Middle layers (M5–M6) for semi-global: Longer signal buses (data buses, global control signals) use intermediate layers for a compromise between resistance and routing density.
Lower layers for signals: M2–M5 carry local connections between nearby cells. Signal nets are typically short (few hundred µm) so the higher resistance of thinner lower-layer metal is acceptable. Also, signals don't need low-resistance routing — RC delay is budgeted in timing analysis.
Middle layers (M5–M6) for semi-global: Longer signal buses (data buses, global control signals) use intermediate layers for a compromise between resistance and routing density.
Why does timing often degrade after routing compared to post-placement estimates?
Post-placement timing uses estimated RC from ideal wire models (e.g., Elmore delay estimate from HPWL). Post-routing uses actual extracted parasitics from real wire shapes — which are always worse than the estimate because:
(1) Wire detours: Router must avoid blockages, other wires, and DRC constraints, so actual wirelength is longer than the HPWL estimate (typically 10–30% longer).
(2) Via resistance: Each via adds resistance; multiple vias on a path compound.
(3) Coupling capacitance: Actual parallel wire runs add coupling capacitance not present in the pre-route estimate.
(4) Layer assignment: If a net is routed on a lower (thinner) layer than assumed, resistance is higher.
This is why post-placement timing targets WNS ≥ −200ps, leaving margin for the 50–300ps degradation that typically occurs after routing.
(1) Wire detours: Router must avoid blockages, other wires, and DRC constraints, so actual wirelength is longer than the HPWL estimate (typically 10–30% longer).
(2) Via resistance: Each via adds resistance; multiple vias on a path compound.
(3) Coupling capacitance: Actual parallel wire runs add coupling capacitance not present in the pre-route estimate.
(4) Layer assignment: If a net is routed on a lower (thinner) layer than assumed, resistance is higher.
This is why post-placement timing targets WNS ≥ −200ps, leaving margin for the 50–300ps degradation that typically occurs after routing.