1. What is Physical Sign-off?
Sign-off is the comprehensive verification stage that confirms the physical layout is correct, manufacturable, and functionally equivalent to the design intent. A chip that passes all sign-off checks is called "silicon-ready."
DRC
Geometric correctness — wire widths, spacings, via enclosures. Tool: Calibre DRC, Synopsys Pegasus.
LVS
Connectivity match between layout and schematic. Finds missing connections, extra connections, swapped pins.
STA
Timing closure at all PVT corners — setup, hold, max transition, max capacitance. Tool: PrimeTime, Tempus.
IR Drop
Voltage drop across power grid — static + dynamic analysis. Ensures cells get adequate Vdd.
EM Check
Wire current density check — ensures wires won't corrode over the product lifetime (10+ years).
ERC
Electrical Rule Check — floating gates, ESD protection, power/ground shorts. Catches functional errors not caught by DRC.
2. DRC — Design Rule Check
DRC verifies that every geometric shape in the layout conforms to the foundry's process design rules (PDK). DRC does NOT verify functionality — only geometric correctness.
| DRC Category | What It Checks | Typical Limit (5nm example) |
|---|---|---|
| Minimum width | Wire or shape narrower than allowed | M1 min width = 24nm |
| Minimum spacing | Two same-layer shapes too close | M1 min spacing = 24nm |
| Minimum area | Metal shape too small (floating metal) | M1 min area = 0.05µm² |
| Via enclosure | Metal doesn't extend enough past via | Enclosure = 4nm each side |
| Via-to-via spacing | Two vias on same via layer too close | V1-V1 = 16nm |
| N-well spacing | N-well to P-well (or N-well to N-well) | Varies by process |
| Density rules | Metal fill density must be within [min, max] range for CMP | e.g., 20%–80% per tile |
| Double patterning | Coloring conflicts (7nm and below) | Depends on litho mask |
DRC = "Will it fabricate correctly?" — Tool: Mentor Calibre DRC (industry standard), Synopsys Pegasus. Must run on the exact GDSII stream that goes to the foundry. Even one DRC violation can cause wafer rejection.
3. LVS — Layout vs Schematic
LVS extracts a netlist from the physical layout (by tracing connectivity through all metal layers and vias) and compares it to the reference schematic netlist from synthesis. It verifies that what was drawn is electrically equivalent to what was designed.
| LVS Error Type | Cause | Fix |
|---|---|---|
| Open | Missing connection in layout — net not connected | Add missing wire/via in ECO |
| Short | Two nets shorted in layout but separate in schematic | Remove incorrect wire, fix DRC violation that caused merge |
| Device mismatch | Wrong transistor type or size in layout vs schematic | Correct the cell or replace with correct variant |
| Port swap | Pin A and pin B swapped at an instance | Fix routing or pin assignment in layout |
| Missing device | Cell instance in schematic not present in layout | Place missing cell and route connections |
4. Final Static Timing Analysis (STA)
Final sign-off STA runs PrimeTime or Tempus on the post-route netlist with full parasitic extraction (SPEF/SPEF-X) at multiple PVT corners to guarantee timing at all operating conditions.
PVT Corners for Sign-off
| Corner | Process | Voltage | Temperature | Check |
|---|---|---|---|---|
| SS (Slow-Slow) | Slow NMOS, Slow PMOS | Vdd_min (−10%) | 125°C | Setup (worst case — slowest) |
| FF (Fast-Fast) | Fast NMOS, Fast PMOS | Vdd_max (+10%) | −40°C | Hold (worst case — fastest) |
| TT (Typical) | Typical NMOS, PMOS | Vdd_nom | 25°C | Both setup + hold (nominal) |
| FS / SF | Fast N / Slow P (or vice versa) | Varies | Varies | Path-specific violations |
STA Sign-off Checks
| Check | What It Verifies | Target |
|---|---|---|
| Setup (max delay) | Data arrives before clock edge − setup_margin | WNS ≥ 0, TNS = 0 |
| Hold (min delay) | Data doesn't arrive too fast (before previous edge clears) | Hold slack ≥ 0 on all paths |
| Max transition | Signal rise/fall time within library limit | 0 max_tran violations |
| Max capacitance | Net load capacitance within drive limit | 0 max_cap violations |
| Glitch / noise | SI noise-induced glitches don't cause functional errors | Noise margin satisfied |
SPEF (Standard Parasitic Exchange Format) is the file that captures extracted RC parasitics for all nets after routing. Sign-off STA reads SPEF to use actual wire delays instead of estimated delays.
5. IR Drop Analysis
The power distribution network (PDN) has resistance. When cells draw current, Ohm's law creates a voltage drop: V_drop = I × R_PDN. Cells with insufficient Vdd run slower, causing timing violations — or fail entirely at very low voltage.
IR Drop = I_cell × R_PDN < 10% × Vdd (typical limit: 100mV for 1V supply)
6. Electromigration (EM)
Electromigration is the gradual movement of metal atoms in a conductor caused by high electron current density. Over time (years of operation), this creates voids (open circuits) or hillocks (short circuits), causing chip failure. EM is a reliability concern — the chip might work at day 0 but fail after 5 years of field operation.
Current Density J = I / (W × T) < J_max (foundry limit, e.g., 1 mA/µm for M1)
| EM Category | What's Checked | Typical Limit |
|---|---|---|
| Metal wire EM | Average current through each metal wire segment | ~1 mA/µm for M1, higher for upper metals |
| Via EM | Current through each via (single-via is risky) | Via EM budget depends on via size and metal |
| Power rail EM | VDD/VSS rails carry highest average current | Wider rails needed for high-current paths |
| Clock net EM | Clock wires switch at max frequency — highest peak current | NDR rules (wider wire) help meet EM budget |
EM Fixes
| Fix | Mechanism |
|---|---|
| Widen wire | Increases cross-sectional area → lower current density |
| Add parallel wires | Split current between multiple wires on same or adjacent layers |
| Use double vias | Two vias in parallel halve the current per via — standard practice for all power paths |
| Use higher metal layer | Top metal has larger thickness/width → higher EM limit |
| Buffer insertion | Split long high-current wires with buffers → shorter segments with lower I each |
7. Tapeout Checklist
Before sending the GDSII to the foundry, every item on this checklist must be verified:
✓
DRC clean — Zero violations in Calibre DRC run on final GDSII stream
✓
LVS clean — Layout matches netlist exactly: no opens, no shorts, no device mismatches
✓
STA clean (all corners) — WNS ≥ 0 and TNS = 0 at SS/FF/TT/FS/SF corners, all modes (func, scan, MBIST)
✓
Hold clean — Zero hold violations at FF corner (fastest) with minimum path delays
✓
IR drop <10% Vdd — Static + dynamic IR drop analysis passes for all power domains
✓
EM clean — All wire and via current densities below foundry limits for 10-year reliability
✓
Antenna clean — All antenna ratios within foundry limits (diodes or jumpers inserted as needed)
✓
ERC clean — No floating gate inputs, ESD protection present on all I/O pads
✓
Metal density — All layers within foundry min/max density for CMP uniformity
✓
Chip-level DRC — Includes metal fill, bond pad rules, seal ring, scribe line
✓
GDSII stream check — Correct layer mapping, no cell name conflicts, GDS merge verified
✓
Simulation signoff — RTL sim, gate-sim, and post-layout sim passing for all target test cases
8. Interview Questions & Answers
What are the key sign-off checks before tapeout?
The mandatory sign-off checks before sending GDSII to the foundry are:
DRC (Design Rule Check): Geometric correctness — wire widths, spacings, via rules per PDK
LVS (Layout vs Schematic): Layout connectivity matches golden netlist — no opens, shorts, device mismatches
STA (Static Timing Analysis): Setup and hold timing at all PVT corners with real extracted parasitics
IR Drop: Power supply voltage within tolerance (<10% Vdd drop) across the entire chip
Electromigration (EM): Wire current density within foundry reliability limits for product lifetime
Antenna check: All antenna ratios below foundry limits
ERC: No floating gates, correct ESD protection
All must show zero violations before tapeout authorization.
DRC (Design Rule Check): Geometric correctness — wire widths, spacings, via rules per PDK
LVS (Layout vs Schematic): Layout connectivity matches golden netlist — no opens, shorts, device mismatches
STA (Static Timing Analysis): Setup and hold timing at all PVT corners with real extracted parasitics
IR Drop: Power supply voltage within tolerance (<10% Vdd drop) across the entire chip
Electromigration (EM): Wire current density within foundry reliability limits for product lifetime
Antenna check: All antenna ratios below foundry limits
ERC: No floating gates, correct ESD protection
All must show zero violations before tapeout authorization.
What is the difference between DRC and LVS?
DRC (Design Rule Check) verifies that every geometric shape in the GDSII layout satisfies the foundry's manufacturing rules — minimum widths, spacings, layer overlaps, via enclosures. It does NOT look at what the circuit does — only at the shapes.
LVS (Layout vs Schematic) extracts a netlist from the physical layout by tracing all metal connections and identifying transistors from their geometry. It then compares this extracted netlist against the reference (golden) schematic from synthesis. If they match electrically (same connections, same device types), LVS passes. If not — missing wire, extra wire, wrong device — LVS fails with a specific error report.
Together: DRC = "will it manufacture?" + LVS = "will it function as designed?"
LVS (Layout vs Schematic) extracts a netlist from the physical layout by tracing all metal connections and identifying transistors from their geometry. It then compares this extracted netlist against the reference (golden) schematic from synthesis. If they match electrically (same connections, same device types), LVS passes. If not — missing wire, extra wire, wrong device — LVS fails with a specific error report.
Together: DRC = "will it manufacture?" + LVS = "will it function as designed?"
What is IR drop and how does it affect timing?
IR drop = voltage lost across the power distribution network resistance: V_drop = I × R_PDN. A cell that should see 1.0V Vdd may only see 0.9V due to resistance in power rings, straps, and rails.
Timing impact: Cell delay depends on supply voltage — lower Vdd → slower logic → longer propagation delay → setup violations. A 10% Vdd reduction can cause ~15–20% longer cell delays in advanced nodes. IR drop must be below 10% Vdd (100mV for 1V supply) for timing to hold.
Two types: (1) Static IR drop — average current flowing through PDN. (2) Dynamic IR drop — simultaneous switching of many cells creates momentary current surge → voltage dip on the supply. Dynamic IR drop is harder to fix and requires decap cells for local charge storage.
Timing impact: Cell delay depends on supply voltage — lower Vdd → slower logic → longer propagation delay → setup violations. A 10% Vdd reduction can cause ~15–20% longer cell delays in advanced nodes. IR drop must be below 10% Vdd (100mV for 1V supply) for timing to hold.
Two types: (1) Static IR drop — average current flowing through PDN. (2) Dynamic IR drop — simultaneous switching of many cells creates momentary current surge → voltage dip on the supply. Dynamic IR drop is harder to fix and requires decap cells for local charge storage.
What is electromigration and how is it fixed during sign-off?
Electromigration (EM) is the physical displacement of metal atoms in a wire caused by momentum transfer from electron flow (high current density). Over years of operation, this creates voids (opens) or hillocks (shorts), causing chip failure. It's a reliability concern, not a day-0 failure.
EM criterion: J = I/(W×T) where W = wire width, T = wire thickness. Foundries specify maximum J (e.g., 1 mA/µm for M1) for 10-year lifetime at operating temperature.
Sign-off fix: The EM analysis tool (Redhawk, Voltus) reports wires violating J_max. Fixes: (1) Widen the wire to reduce J, (2) Add a parallel wire on adjacent layer to share current, (3) Use double vias (halve per-via current), (4) Insert buffer to split a long high-current net into shorter segments.
EM criterion: J = I/(W×T) where W = wire width, T = wire thickness. Foundries specify maximum J (e.g., 1 mA/µm for M1) for 10-year lifetime at operating temperature.
Sign-off fix: The EM analysis tool (Redhawk, Voltus) reports wires violating J_max. Fixes: (1) Widen the wire to reduce J, (2) Add a parallel wire on adjacent layer to share current, (3) Use double vias (halve per-via current), (4) Insert buffer to split a long high-current net into shorter segments.
Why do we run STA at multiple PVT corners and which corner catches which violation?
Process (P), Voltage (V), and Temperature (T) all affect transistor speed and wire resistance. A chip must work correctly across all operating conditions it will see in the field.
SS (Slow-Slow) corner — catches setup violations: Slow process (longer gate delay) + low voltage (slower switching) + high temperature (reduced carrier mobility) → worst-case long path delays. If setup passes here, it passes everywhere for long paths.
FF (Fast-Fast) corner — catches hold violations: Fast process + high voltage + low temperature → shortest possible path delays. Hold violations occur when data arrives too soon. If hold passes here, it passes at all conditions.
TT (Typical): Nominal conditions — used for power estimation and sanity checks.
FS/SF (mixed corners): Catch path-specific violations where NMOS and PMOS don't track together — important for complex logic paths.
SS (Slow-Slow) corner — catches setup violations: Slow process (longer gate delay) + low voltage (slower switching) + high temperature (reduced carrier mobility) → worst-case long path delays. If setup passes here, it passes everywhere for long paths.
FF (Fast-Fast) corner — catches hold violations: Fast process + high voltage + low temperature → shortest possible path delays. Hold violations occur when data arrives too soon. If hold passes here, it passes at all conditions.
TT (Typical): Nominal conditions — used for power estimation and sanity checks.
FS/SF (mixed corners): Catch path-specific violations where NMOS and PMOS don't track together — important for complex logic paths.
What is an Engineering Change Order (ECO) and when is it used during sign-off?
An ECO (Engineering Change Order) is a targeted post-route change to fix a specific violation without re-running the full PnR flow. ECOs are used when sign-off reveals a small number of violations that can be fixed locally:
Timing ECO: Insert a buffer or resize a cell on a critical path to fix a remaining setup violation. Only affects the critical path, not the rest of the chip.
DRC ECO: Fix a handful of DRC violations by rerouting specific wire segments manually or with a DRC-fix ECO router.
Functional ECO: Change a few logic cells (e.g., replace AND with NAND+INV) to fix a design bug found late.
ECOs are expensive: changes must be re-extracted for parasitics, re-signed-off for DRC/LVS, and re-verified for timing. Multiple ECO iterations delay tapeout significantly. The goal of a good sign-off flow is to minimize ECOs.
Timing ECO: Insert a buffer or resize a cell on a critical path to fix a remaining setup violation. Only affects the critical path, not the rest of the chip.
DRC ECO: Fix a handful of DRC violations by rerouting specific wire segments manually or with a DRC-fix ECO router.
Functional ECO: Change a few logic cells (e.g., replace AND with NAND+INV) to fix a design bug found late.
ECOs are expensive: changes must be re-extracted for parasitics, re-signed-off for DRC/LVS, and re-verified for timing. Multiple ECO iterations delay tapeout significantly. The goal of a good sign-off flow is to minimize ECOs.