Datapath Overview — Fetch, Decode, Execute

Phase 1 gave you the instruction set. Phase 2 is where the real fun starts: we build the hardware that runs it. This lesson gives you the complete picture of the single-cycle RISC-V CPU — every component, every stage, every wire — before we implement each piece. By the end you'll have the datapath diagram in your head and the first real CPU module, the Program Counter, running in Verilog.

1. The big idea: what a CPU really is

Strip away the marketing. A CPU is just a machine that repeats one loop forever:

1. Fetch an instruction from memory at the current address.
2. Decode it — figure out what kind of instruction it is and which registers it needs.
3. Execute it — compute the result.
4. Access memory — if it's a load or store.
5. Write back the result to a register.
6. Advance the program counter. Go back to step 1.

That loop is what every piece of the datapath serves. Let's map the hardware to the loop.

2. The five stages, one at a time

In a single-cycle CPU all five stages happen in one clock cycle — no pipeline registers, no stalls. It's slower than a pipeline but far simpler to understand and build. Once this works, pipelining it is a natural next step.

3. Every component on the datapath

4. The full datapath — wired together

5. Tracing one instruction through the datapath

Let's walk add x3, x1, x2 through every stage:

At the end of the cycle, PC ← PC+4 (no branch taken) and the loop repeats.

6. Build it: the Program Counter (pc.v)

Every journey starts with the PC. It's the simplest module: a 32-bit register that latches pc_next on every rising clock edge, and resets to 0.

Port table:

// Program Counter — 32-bit register, synchronous reset
module pc (
    input  wire        clk,      // clock
    input  wire        rst,      // synchronous reset (active high)
    input  wire [31:0] pc_next,  // next PC value (PC+4 or branch target)
    output reg  [31:0] pc        // current PC value → IMEM address
);
    always @(posedge clk) begin
        if (rst) pc <= 32'h0000_0000;
        else     pc <= pc_next;
    end
endmodule

7. Test it: testbench (tb_pc.v)

A self-checking testbench: reset the PC, then step through several cycles and verify the address advances correctly:

`timescale 1ns/1ps
module tb_pc;
    reg        clk, rst;
    reg [31:0] pc_next;
    wire[31:0] pc;

    pc dut (.clk(clk), .rst(rst), .pc_next(pc_next), .pc(pc));

    // 10 ns clock
    initial clk = 0;
    always #5 clk = ~clk;

    integer errors = 0;
    task check(input [31:0] exp);
        if (pc !== exp) begin
            $display("FAIL: pc=%0h expected=%0h", pc, exp);
            errors = errors + 1;
        end else
            $display("ok:   pc=%0h", pc);
    endtask

    initial begin
        // --- reset ---
        rst=1; pc_next=32'h0; @(posedge clk); #1;
        check(32'h0000_0000);    // after reset, PC=0

        // --- advance PC+4 each cycle ---
        rst=0;
        pc_next=32'h0000_0004; @(posedge clk); #1; check(32'h0000_0004);
        pc_next=32'h0000_0008; @(posedge clk); #1; check(32'h0000_0008);
        pc_next=32'h0000_000C; @(posedge clk); #1; check(32'h0000_000C);

        // --- branch jump to address ---
        pc_next=32'h0000_0100; @(posedge clk); #1; check(32'h0000_0100);

        // --- reset again ---
        rst=1; pc_next=32'h0; @(posedge clk); #1; check(32'h0000_0000);

        if (errors==0) $display("ALL TESTS PASSED");
        else           $display("%0d TEST(S) FAILED", errors);
        $finish;
    end
endmodule

iverilog -o pc_tb pc.v tb_pc.v
vvp pc_tb

Expected output:

ok:   pc=00000000
ok:   pc=00000004
ok:   pc=00000008
ok:   pc=0000000c
ok:   pc=00000100
ok:   pc=00000000
ALL TESTS PASSED

Quick check

1. Name the five stages of the single-cycle RISC-V pipeline.
2. Which component decides whether the next PC is PC+4 or a branch target?
3. What does the ALUMUX select between?
4. Why does the write-back path loop back from right to left in the datapath?

FAQ

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