Why did the iPhone 6s use custom NVMe storage over PCIe?

The iPhone 6s was the first smartphone in history to bypass standard eMMC/UFS flash memory, embedding an Apple-designed custom NVMe storage controller ASIC communicating over a high-speed PCIe 2.0 x1 lane. This unlocked sequential read speeds above 400 MB/s and deep command queuing, dramatically reducing app launch latencies.

What was the A9 'Chipgate' dual-sourcing event?

To fulfill massive global demand at launch, Apple contracted two rival foundries: Samsung manufactured the A9 (APL0898) on its 14nm FinFET LPE process (96 mm² die), while TSMC produced the A9 (APL1022) on its 16nm FinFET FF+ process (104.5 mm² die). Despite minor physical dimension differences, both delivered practically identical real-world battery life and compute performance.

How does the iPhone 6s Taptic Engine differ from traditional phone vibrators?

Traditional phones used an Eccentric Rotating Mass (ERM) motor requiring 50-100 ms to spin up. The Taptic Engine is a Linear Resonant Actuator (LRA) driven by copper voice coils that propels a high-density tungsten mass linearly with electromagnetic reverse-phase braking in under 10 ms, producing crisp tactile sensations for 3D Touch.

Apple iPhone 6s — Physical Teardown

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A9 Dual Foundry Analysis ("Chipgate")

Samsung 14nm FinFET (APL0898): 96.0 mm² die size with 78nm contacted poly pitch. Smaller physical footprint due to denser standard-cell library layout.

TSMC 16nm FinFET (APL1022): 104.5 mm² die size with 90nm contacted poly pitch. Slightly larger physical area, but exhibited marginally cooler sustained thermal leakage in real-world endurance tests.

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The Engineering Legacy of the Apple iPhone 6s

Released on September 25, 2015, the Apple iPhone 6s (internal codename N71 / N66) represents one of the most consequential inflection points in consumer electronics and semiconductor history. Beyond its external 7000-series aerospace aluminum shell and pressure-sensitive 3D Touch display, the phone pioneered architectural leaps that permanently transformed mobile silicon design: the industry's first desktop-grade 6-wide superscalar CPU core (Twister), the first custom mobile NVMe storage architecture over PCIe, and the historic "Chipgate" dual-sourcing across Samsung 14nm and TSMC 16nm FinFET foundries.

1. Structural Metallurgy: The 7000-Series Aerospace Aluminum Chassis

Following the mechanical deflection concerns of the iPhone 6 ("bendgate"), Apple overhauled its chassis metallurgy for the 6s. The unibody enclosure is precision CNC-machined from a solid extruded billet of 7000-series zinc-alloy aluminum (Al-Zn-Mg-Cu). With a yield strength exceeding 300 MPa—over 60% stronger than standard 6000-series architectural alloys—the unibody provides extreme torsional rigidity while acting as the system's primary thermal heatsink and ground plane.

Precision-milled antenna isolation strips (co-molded with high-dielectric polymers) segment the perimeter into distinct resonant dipole antennas for multi-band LTE, dual-band Wi-Fi, Bluetooth 4.2, and NFC, preventing the user's hand from detuning the RF transceiver.

2. Actuator Physics: The Taptic Engine & 3D Touch Capacitive Grid

The iPhone 6s introduced 3D Touch, a dual-layer human interface system. Beneath the 4.7-inch Retina HD LCD panel (1334 × 750 pixels @ 326 ppi) lies an array of 96 microscopic capacitive sensors embedded within the backlight stack. When a user presses the flexible Ion-X cover glass, the micro-deflection alters the distance between the glass and the sensor grid, generating sub-picofarad capacitance variations sampled at 240 Hz.

To provide instantaneous tactile feedback for "Peek" and "Pop" gestures, Apple eliminated conventional Eccentric Rotating Mass (ERM) motors and engineered the Taptic Engine: a custom Linear Resonant Actuator (LRA). A high-density sintered tungsten mass is suspended on laser-welded spring flexures and driven by copper voice coils. Driven by a dedicated Cirrus Logic Class-D amplifier, the mass reaches its peak vibration amplitude within a single oscillation cycle (under 10 milliseconds) and utilizes active reverse-phase electromagnetic braking to stop instantly, creating an unmistakable tactile sensation indistinguishable from an actual mechanical click.

3. Logic Board Architecture: 10-Layer Any-Layer HDI PCB

The iPhone 6s motherboard adopts an L-shaped form factor designed to maximize battery volume. Fabricated by AT&S and Compeq, the board is a 10-layer High-Density Interconnect (HDI) printed circuit board utilizing laser-drilled staggered and stacked microvias with an Electroless Nickel Immersion Gold (ENIG) surface finish. With line widths and spaces under 50 microns, the board allows the 1,000+ ball grid array of the Apple A9 to escape cleanly without causing parasitic inductive ringing or signal integrity degradation across high-speed LPDDR4, PCIe, and MIPI data lines.

4. Apple A9 SoC: The 6-Wide Superscalar Desktop Core in Your Pocket

At the center of the iPhone 6s sits the Apple A9 Application Processor. While contemporaneous mobile competitors (such as the Qualcomm Snapdragon 810) pursued eight smaller ARM Cortex-A53/A57 cores in a big.LITTLE configuration, Apple designed its own custom 64-bit ARMv8-A core: Twister.

6-Wide Instruction Decode: Twister could fetch, decode, and rename up to 6 instructions per clock cycle—a decode width wider than contemporaneous Intel Core M laptop processors.
192-Entry Reorder Buffer (ROB): A massive out-of-order execution window that allowed the core to extract deep Instruction-Level Parallelism (ILP), keeping 4 integer ALUs, 2 Branch units, and 2 NEON SIMD floating-point engines continuously saturated.
Cache Hierarchy: Each core features private 64 KB L1 Instruction and 64 KB L1 Data caches operating with ultra-low 3-cycle latency, backed by a unified 3 MB 16-way associative L2 cache.
8 MB System Level Cache (SLC): An on-die SRAM buffer shared between the CPU, PowerVR GT7600 GPU, and Image Signal Processor (ISP). Because accessing external DRAM consumes ~100× more energy per bit than on-die SRAM, the SLC absorbed up to 50% of memory requests, preserving battery life and eliminating memory bandwidth bottlenecks.

5. The "Chipgate" Dual-Foundry Sourcing: Samsung 14nm vs TSMC 16nm

Due to the staggering volume of iPhone 6s units required at launch (selling over 13 million units in its opening weekend), no single foundry possessed enough leading-edge FinFET wafer capacity. Apple executed an unprecedented engineering feat: synthesizing the identical digital RTL design into two distinct physical libraries across two competing foundries:

Samsung 14nm FinFET (APL0898): Die area of 96.0 mm² (9.6 × 10.0 mm) with a 78nm contacted poly pitch and 64nm metal pitch. Transistor density reached approximately 32.5 MTr/mm².
TSMC 16nm FinFET (APL1022): Die area of 104.5 mm² (10.1 × 10.3 mm) with a 90nm contacted poly pitch and 64nm metal pitch. Transistor density was approximately 29.8 MTr/mm².

While tech enthusiasts subjected both variants to torture tests that sparked intense internet debate ("Chipgate"), rigorous real-world battery benchmarks revealed less than a 2–3% variance across typical mixed workloads—well within standard Li-ion battery manufacturing tolerances.

6. Mobile Storage Revolution: Custom PCIe NVMe Controller

Prior to the iPhone 6s, the mobile industry relied universally on eMMC or early UFS flash interfaces, which handled storage commands over narrow serial queues. Apple broke with the entire smartphone industry by embedding a custom-designed NVMe ASIC controller inside the NAND flash package, connecting directly to the A9 SoC over a high-speed PCIe 2.0 x1 lane.

With deep hardware command queuing, direct memory access (DMA), and dedicated Low-Density Parity-Check (LDPC) error correction engines, the iPhone 6s achieved sequential read speeds surpassing 400 MB/s—over triple the speed of rival flagship devices. This single architectural decision eliminated UI stuttering, accelerated app loading, and made instantaneous 4K video recording possible.