SystemVerilog for Verification

Most RTL engineers know how to build hardware. Far fewer know how to verify it properly. SystemVerilog is the language of professional chip verification — and UVM is the methodology every semiconductor company uses. This course teaches both from scratch.

▶ Start with Day 1 — Why SystemVerilog?

Who this is for: Engineers who know Verilog and want to break into verification, or RTL designers who want to write proper testbenches. No prior SystemVerilog knowledge needed.

What you'll build: A complete UVM testbench for a real AXI-Lite slave — from a basic simulation to a coverage-driven, constrained-random, self-checking environment.

PHASE 1

SystemVerilog Fundamentals

Day 1Why SystemVerilog? What Verilog can't doLive Day 2Data types — logic, bit, byte, int, shortrealLive Day 3Packed & unpacked arrays, queues, associative arraysLive Day 4Tasks, functions and automatic lifetimeLive Day 5Interfaces & modports — clean testbench connectionsLive Day 6Clocking blocks & synchronisationLive

PHASE 2

Object-Oriented Programming in SV

Day 7Classes, objects and handlesLive Day 8Inheritance, polymorphism, virtual methodsLive Day 9Parameterised classes & factoriesLive Day 10Mailboxes, semaphores & eventsLive Day 11Threads — fork/join, disable, fine-grain controlLive

PHASE 3

Constrained Random & Coverage

Day 12Randomisation & constraints — rand, constraint blocksLive Day 13Functional coverage — covergroup, coverpoint, crossLive Day 14Advanced coverage — exclusions, gaps, closureLive Day 15Coverage metrics and regression monitoringLive Day 16Coverage-driven test generationLive

PHASE 4

Assertions (SVA)

Day 17Assertions basics — immediate & concurrentLive Day 18Advanced SVA — sequences, repetition, operatorsLive Day 19Assertion coverage & debuggingLive Day 20Binding & controlling assertionsLive

PHASE 5

The UVM Methodology

Day 21UVM introduction — phases & architectureLive Day 22UVM components — drivers, monitors, agentsLive Day 23Scoreboards & automated checkingLive Day 24Config database & parameter passingLive Day 25🎉 Complete UVM testbench & methodology reviewLive

New lessons publish regularly. Pair with RISC-V from Scratch, FPGA from Scratch, and the VLSI Design Hub.