An MMU, or Memory Management Unit, is hardware that translates the virtual addresses used by software into the physical addresses of real memory. It does this using page tables, lets each process have its own private virtual address space, and enforces access permissions, enabling virtual memory in rich operating systems like Linux on ARM Cortex-A processors.

What is virtual memory?

Virtual memory is an abstraction where each program sees a large, private, contiguous address space that the MMU maps onto physical RAM, possibly backed by disk. It gives isolation between processes, lets programs use more memory than is physically present through paging, and simplifies how programs are loaded and shared.

A TLB, or Translation Lookaside Buffer, is a small fast cache inside the MMU that stores recently used virtual-to-physical translations. Because walking the page tables in memory is slow, the TLB lets the vast majority of translations complete in a single cycle. A TLB miss triggers a page-table walk to fetch the mapping.

What is the difference between an MMU and an MPU?

An MPU only enforces access permissions on a few fixed regions of the physical address space and does no translation. An MMU performs full virtual-to-physical translation with fine-grained page tables and gives each process its own virtual address space. MMUs are used in application processors like Cortex-A; MPUs are used in real-time microcontrollers like Cortex-M.

DAY 21 · SYSTEM & MEMORY

The MMU & Virtual Memory

By EcrioniX · Updated Jun 6, 2026

How can two programs both use address 0x8000 without colliding? How can a program "see" more memory than the chip physically has? The answer to both is one of the most elegant ideas in computing: virtual memory, made real by the MMU. This is the hardware that turns a microcontroller into a computer that can run Linux.

1. The big idea: a layer of indirection

Every address your program uses is a virtual address. It is not the real location in RAM. Between the CPU and memory sits the MMU (Memory Management Unit), which translates each virtual address into a physical address on the fly, for every single access.

That one layer of indirection buys an astonishing amount:

Isolation — every process gets its own private address space; one app literally cannot name another's memory.
The illusion of more memory — addresses can map to RAM, or to disk (paging), so programs can use more than the physical RAM.
Flexibility — code can be loaded anywhere physically while always appearing at the same virtual address.

2. Pages and page tables

Translating every byte individually would be impossible, so memory is divided into fixed-size chunks called pages (commonly 4 KB). The MMU only needs to map page → page. The map itself is the page table, stored in memory: one entry per virtual page giving its physical frame plus permission bits.

Figure — The low bits (offset within a page) pass through unchanged; the MMU only translates the page number.

A flat table for a 4 GB space would be huge, so ARM uses multi-level page tables (a tree). The CPU register TTBR (Translation Table Base Register) points to the current process's top-level table — switching it is how the OS switches address spaces on a context switch.

3. The TLB — making it fast

Walking a multi-level table means several memory reads per access — far too slow if done every time. So the MMU caches recent translations in the TLB (Translation Lookaside Buffer), a small, very fast lookup. Most accesses hit the TLB and translate in effectively one cycle; a miss triggers a page-table walk to fetch and cache the mapping.

💡 Hotel front desk

The page table is the hotel's full guest register in the back office. The TLB is the receptionist's sticky notes for the guests who came by in the last minute. Most lookups are answered instantly from the notes; only an unfamiliar name needs a trip to the back office.

4. Page faults & demand paging

What if a virtual page isn't currently in RAM, or you touch one you're not allowed to? The MMU raises a page fault — an exception (Day 17) handled by the OS. The OS decides what to do:

Demand paging — the page is on disk; load it into a free frame, fix the table, and retry the instruction. The program never knows it waited.
Copy-on-write — a shared page was written; make a private copy first.
Real bug — a genuinely invalid access → segmentation fault, kill the process.

This is how a system "runs more than its RAM": rarely used pages live on disk and are paged in on demand.

5. MMU vs MPU

	MPU (Day 20)	MMU (today)
Translation	none (physical only)	virtual → physical
Granularity	a few regions	fine-grained pages
Per-process space	no	yes
Typical core	Cortex-M / R	Cortex-A
Runs	bare-metal / RTOS	Linux, Android, rich OS

The MPU only protects; the MMU translates and protects. That extra power is exactly what a general-purpose OS needs.

✅ The mental model

The MMU sits between CPU and RAM and translates every virtual address to a physical one using page tables, cached by the TLB for speed. This gives each process a private address space, lets the OS use disk as overflow via page faults, and is the dividing line between a microcontroller (MPU) and a full computer (MMU).

🎯 Day 21 takeaways

The MMU translates virtual → physical addresses on every access.
Memory is split into pages (e.g. 4 KB); the page table (multi-level) holds the map.
TTBR points at the active table; switching it switches address spaces.
The TLB caches translations; a miss causes a page-table walk.
Page faults enable demand paging, copy-on-write — or catch real bugs.

Quick check

Why does the offset within a page not need translating?
What does the TLB cache, and what happens on a TLB miss?
Name one useful thing a page fault lets the OS do.

FAQ

What is an MMU?

Hardware that translates virtual addresses to physical ones via page tables, giving each process a private address space.

What is the TLB?

A fast cache of recent virtual-to-physical translations; a miss triggers a page-table walk.

MMU vs MPU?

The MPU only protects fixed physical regions; the MMU also translates with fine-grained pages and per-process spaces.

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