"ARM assembly" isn't one language — it's a small family. Today we meet all four members, learn why several exist (it comes down to a single trade-off: code size vs performance), and see which cores speak which.
Every instruction takes space in memory. Wider instructions can do more per line but make programs bigger; narrower instructions are smaller but each does less. On a cheap microcontroller with tiny flash, code size is precious. On a high-end core, raw performance matters more. ARM's instruction sets are different answers to that one tension.
The original. Powerful, expressive, every instruction conditional. Larger code. AArch32 only.
A compact subset — common ops in half the space. Great density, slightly less power per instruction.
The sweet spot: mixes 16- & 32-bit. Thumb's size with near-ARM performance. Cortex-M uses this.
The 64-bit ARMv8 set. Clean redesign, 31 registers. Phones, laptops, servers run this.
Fixed 32-bit instructions. Rich and regular: almost every instruction can be conditionally executed (a neat ARM trick we cover on Day 11) and can fold in a shift for free (the barrel shifter, Day 9). The downside: every instruction is 4 bytes, so programs are relatively large. Exists only in the 32-bit (AArch32) world.
To cut code size, ARM added Thumb: the most-used operations re-encoded in just 16 bits. That roughly halves code size — a huge win for memory-constrained devices — at the cost of each instruction doing a little less and using fewer registers directly. Early mobile and embedded chips leaned on Thumb heavily.
Pure 16-bit Thumb was too limiting for everything. Thumb-2 fixed that by freely mixing 16-bit and 32-bit instructions: the common stuff stays 16-bit (small), the rest uses 32-bit forms (powerful). Result — Thumb's density with nearly ARM's performance. It was such a good compromise that Cortex-M cores run Thumb-2 exclusively — they don't even implement the old A32 state.
Texting. ARM = always writing full sentences (clear, but long). Thumb = abbreviations only (short, but limited). Thumb-2 = abbreviate the common words, spell out the rare ones — short and expressive.
With ARMv8, ARM introduced AArch64 and a brand-new instruction set, A64. It's not an extension of the old sets — it's a clean redesign: fixed 32-bit instruction width, 31 general-purpose 64-bit registers (X0–X30), and dropped some legacy quirks (most instructions are no longer conditional). This is what 64-bit phones, Apple Silicon Macs, and ARM servers execute. We'll dive into AArch64 properly on Day 26.
In the 32-bit world, a single bit — the T bit in the CPSR (remember Day 3?) — selects ARM vs Thumb state, and a special branch (BX) can switch between them ("interworking"). AArch64 is its own execution state entirely.
| Core family | Instruction set(s) |
|---|---|
| Cortex-M (microcontroller) | Thumb / Thumb-2 (T32) only |
| Cortex-R (real-time) | A32 + T32 |
| Cortex-A (application, 32-bit) | A32 + T32 |
| Cortex-A / Neoverse (64-bit) | A64 (and A32/T32 in 32-bit mode where supported) |
The assembly reads almost the same — but the bits in memory, the register width, and the capabilities differ. As a beginner you mostly write the mnemonics; the assembler picks the right encoding for your target.
A32 = original 32-bit, big & powerful. Thumb = 16-bit, tiny. Thumb-2 = mixed, the practical winner (Cortex-M). A64 = the 64-bit redesign for modern high-performance ARM.
BX switches.A32 is fixed 32-bit (powerful, larger). Thumb is 16-bit (compact). Thumb-2 mixes both for density + performance.
T32 — an instruction set mixing 16- and 32-bit instructions; Cortex-M runs it exclusively.
The 64-bit ARMv8 instruction set (AArch64): fixed 32-bit encoding, 31 registers, a clean modern redesign.