DAY 7 · THE INSTRUCTION SET

The Pipeline — How an Instruction Actually Flows

We've met the registers and the data. Now: how does the CPU execute instructions fast? The answer is the pipeline — an assembly line for instructions, and the single most important idea behind processor performance.

1. The assembly-line idea

Executing one instruction takes several steps: fetch it from memory, decode what it means, then execute it. Done one-at-a-time, the fetch and decode hardware sits idle while the execute hardware works, and vice-versa. Wasteful.

So pipelining overlaps them: while instruction 1 executes, instruction 2 is being decoded, and instruction 3 is being fetched — three instructions in flight at once, every stage busy every cycle.

2. Latency vs throughput

This distinction is the whole point:

• Latency — how long one instruction takes start-to-finish (still several cycles).
• Throughput — how often a finished instruction pops out. With a full pipeline: one per cycle, even though each took several.

Pipelining doesn't make a single instruction faster — it makes the stream of instructions flow at roughly one per clock. That's a several-times speedup for the same hardware.

3. The classic ARM pipelines

Early ARM (ARM7) used a 3-stage pipeline:

Cycle →	1	2	3	4	5
Instr 1	F	D	E
Instr 2		F	D	E
Instr 3			F	D	E

F=Fetch · D=Decode · E=Execute. From cycle 3 on, one instruction completes every cycle.

ARM9 and later use a 5-stage pipeline, splitting out memory and writeback:

Stage	1	2	3	4	5
Names	Fetch	Decode	Execute	Memory	Writeback

Memory handles load/store data access; Writeback writes the result into the register file. Modern Cortex-A cores go much deeper (10+ stages), superscalar (several instructions per cycle) and out-of-order — but the principle is identical.

4. The famous "PC + 8" quirk

Here's a classic ARM gotcha that the pipeline explains. In the 3-stage pipeline, when an instruction is executing, the PC has already moved on to fetch the instruction two ahead. Since ARM instructions are 4 bytes, the PC reads as the current instruction's address + 8.

This is why PC-relative address calculations account for the offset. (In Thumb state it's +4; the assembler usually handles it for you, but now you know why.)

5. When the pipeline stalls — hazards

The dream of "one instruction per cycle" breaks when an instruction can't proceed. These are hazards:

• Data hazard — an instruction needs a result the previous one hasn't produced yet. Fixed by forwarding (routing the result early) or, failing that, a stall (bubble).
• Control hazard — a branch. The pipeline already fetched the next sequential instructions, but the branch goes elsewhere — so those wrong instructions must be flushed, costing cycles (the branch penalty).
• Structural hazard — two instructions need the same hardware resource in the same cycle.

To soften control hazards, modern cores use branch prediction — guessing the branch outcome and speculatively fetching ahead. A correct guess = no penalty; a wrong guess = flush and refill.

Quick check

1. Does pipelining reduce the latency of a single instruction?
2. In the 3-stage pipeline, why does MOV r0, pc give current address + 8?
3. Why does a deeper pipeline make branch mispredictions more expensive?

FAQ

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