What is the difference between an exception and an interrupt?

An exception is any event that diverts the processor from normal execution to a handler - this includes reset, undefined instructions, memory aborts, software interrupts and hardware interrupts. An interrupt is one kind of exception, raised by external hardware such as a timer or peripheral. So every interrupt is an exception, but not every exception is an interrupt.

What is the difference between IRQ and FIQ in ARM?

IRQ is the normal interrupt request; FIQ is the Fast Interrupt reQuest, given higher priority and designed for low latency. FIQ has more banked registers (r8 to r14), so its handler can run without saving and restoring as many registers, and its vector sits last in the table so the handler can start right there. FIQ is typically reserved for the single most time-critical interrupt source.

What is the exception vector table?

The vector table is a fixed array of entries, one per exception type, that the core jumps to when that exception occurs. In classic ARM each entry is one instruction - usually a branch to the real handler - covering reset, undefined instruction, software interrupt, prefetch abort, data abort, IRQ and FIQ. It usually lives at address 0 and tells the processor where each handler is.

What does the ARM core do automatically when an exception occurs?

On entry the core switches to the appropriate mode, saves the current status register into the SPSR of that mode, stores the return address in the banked link register, disables further interrupts as needed, and jumps to the matching vector. Thanks to banked registers it does this with minimal overhead. Your handler then runs, and a special return instruction restores both the PC and the status register.

DAY 17 · SYSTEM & MEMORY

Exceptions & Interrupts — IRQ, FIQ & the Vector Table

By EcrioniX · Updated Jun 6, 2026

Until now your code ran top to bottom. But real systems must react — a timer fires, a button is pressed, an instruction faults. The mechanism that lets the processor drop everything, handle the event, and resume exactly where it left off is the exception. Get this right and your firmware comes alive.

1. Exception vs interrupt

People use the words interchangeably, but there's a hierarchy:

An exception is any event that diverts the core from normal flow to a special handler — reset, an undefined instruction, a memory abort, a software interrupt (SVC), or a hardware interrupt.
An interrupt is one kind of exception — raised by external hardware (timer, UART, GPIO).

So: every interrupt is an exception, but not every exception is an interrupt.

2. The classic ARM exceptions

Exception	Cause	Mode entered
Reset	power-on / hard reset	Supervisor
Undefined	unknown instruction	Undefined
SVC (SWI)	software interrupt — call into the OS	Supervisor
Prefetch abort	bad instruction fetch	Abort
Data abort	bad data access	Abort
IRQ	normal hardware interrupt	IRQ
FIQ	fast hardware interrupt	FIQ

These tie straight back to the operating modes from Day 5 — each exception drops the core into a specific privileged mode.

3. The vector table

When an exception fires, the core doesn't search for a handler — it jumps to a fixed address reserved for that exception. The block of these fixed addresses is the vector table, usually at address 0x00000000. In classic ARM each slot holds one instruction, almost always a branch to the real handler:

; Classic ARM vector table (one instruction per entry) _vectors: B reset_handler ; 0x00 Reset B undef_handler ; 0x04 Undefined instruction B svc_handler ; 0x08 Software interrupt (SVC) B pabort_handler ; 0x0C Prefetch abort B dabort_handler ; 0x10 Data abort ; 0x14 (reserved) B irq_handler ; 0x18 IRQ B fiq_handler ; 0x1C FIQ ← last, so the handler can start right here

FIQ sits last on purpose: there's nothing after it, so the FIQ handler code can begin immediately at the vector with no extra branch — shaving cycles off the fastest interrupt.

4. IRQ vs FIQ — why two?

	IRQ	FIQ (Fast Interrupt)
Priority	normal	higher
Banked registers	r13, r14	r8–r14 (more)
Latency	low	lowest
Typical use	most peripherals	the one most time-critical source

FIQ has extra banked registers (r8–r14), so its handler has private scratch registers it can use without pushing/popping the interrupted code's values — less save/restore means lower latency. You typically reserve FIQ for a single critical source (e.g. a motor controller) and route everything else through IRQ.

5. What the core does automatically on entry

The hardware does several things for you the instant an exception is taken:

Switches mode (e.g. into IRQ mode), changing which banked SP/LR are visible.
Saves CPSR → SPSR of the new mode, so the old processor state is preserved.
Saves the return address into the mode's banked LR.
Disables further interrupts as appropriate (e.g. masks IRQ; FIQ masks both).
Jumps to the vector for that exception.

Banked registers (Day 5) are what make this cheap — the handler gets its own SP and LR without touching the interrupted program's.

6. Returning from an exception

Returning isn't a plain BX LR, because you must restore both the PC and the saved status (SPSR → CPSR) atomically, and adjust for pipeline offset. ARM provides special forms:

irq_handler: SUB lr, lr, #4 ; adjust return address (IRQ) PUSH {r0-r3, lr} ; save scratch regs we'll use ; ... handle the interrupt (clear the peripheral flag!) ... LDM sp!, {r0-r3, pc}^ ; return: restore regs, PC, and CPSR (the ^)

The ^ on the load-to-PC tells the core to also restore CPSR from SPSR. On Cortex-M this is all handled differently and far more automatically — which is exactly tomorrow's topic, the NVIC.

✅ The mental model

An exception is a hardware-driven function call: the core saves your state, switches to a privileged mode, and jumps to a fixed vector. IRQ is the everyday interrupt; FIQ is the privileged fast lane with extra banked registers. Your handler does the work and returns by restoring both PC and CPSR together.

🎯 Day 17 takeaways

An interrupt is one kind of exception; both divert the core to a handler.
The vector table (at 0x0) holds one entry per exception type.
FIQ > IRQ: higher priority, more banked registers, lowest latency, vector last.
On entry the core auto-saves CPSR→SPSR, return→LR, switches mode, masks interrupts.
Return restores PC + CPSR together (e.g. LDM sp!, {…, pc}^).

Quick check

Why is every interrupt an exception but not vice-versa?
Name two reasons FIQ has lower latency than IRQ.
What does the ^ do on an exception-return LDM?

FAQ

Exception vs interrupt?

An exception is any diversion to a handler (reset, fault, SVC, interrupt); an interrupt is specifically a hardware-raised exception.

IRQ vs FIQ?

FIQ is the fast, higher-priority interrupt with extra banked registers (r8–r14) and its vector last, for the most time-critical source.

What's the vector table?

A fixed array of per-exception entries (usually at 0x0) the core jumps to when an exception occurs.

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