The NVIC, or Nested Vectored Interrupt Controller, is the interrupt controller built into every ARM Cortex-M processor. It manages all interrupt sources, fetches the correct handler address from a vector table in hardware, supports configurable priorities with nesting and preemption, and automatically saves and restores processor state, so an interrupt service routine can be written as an ordinary C function.

Why can a Cortex-M ISR be a plain C function?

Because the NVIC and core automatically push the caller-saved registers (r0 to r3, r12, LR, PC and xPSR) onto the stack on entry and pop them on exit. Since the AAPCS caller-saved set is preserved by hardware, the handler does not need special assembly wrappers, so it follows the normal calling convention and can be written in standard C.

How do interrupt priorities work on Cortex-M?

Each interrupt has a configurable priority number where a lower number means higher priority. A higher-priority interrupt can preempt a running lower-priority handler, creating nested interrupts. Priority is split into preemption and sub-priority fields, and the number of implemented priority bits varies by device, commonly three to eight bits.

DAY 18 · SYSTEM & MEMORY

The NVIC — Interrupts on Cortex-M

Q: What is tail-chaining?

Tail-chaining is an NVIC optimisation where, if a second interrupt is pending when one handler finishes, the core skips the pop-then-push of the stack frame and goes directly into the next handler. This removes redundant stacking work between back-to-back interrupts and significantly lowers latency.

By EcrioniX · Updated Jun 6, 2026

Yesterday's classic-ARM interrupts needed hand-written assembly wrappers to save state. Cortex-M throws all of that away. Its built-in NVIC does the vectoring, the register saving, and the prioritising in hardware — so an interrupt handler becomes nothing more than a normal C function. This is the single biggest reason Cortex-M is so beginner-friendly.

1. What the NVIC is

The NVIC — Nested Vectored Interrupt Controller — is a standard block inside every Cortex-M core. "Nested" = interrupts can interrupt each other by priority. "Vectored" = the hardware fetches the right handler address directly. It manages dozens to hundreds of interrupt sources plus core system exceptions.

2. The Cortex-M vector table

Unlike classic ARM (where each vector was a branch instruction), a Cortex-M vector table is a plain array of function-pointer addresses. Slot 0 is even special: it holds the initial stack pointer, loaded automatically at reset before any code runs.

// Cortex-M vector table = array of addresses (not instructions) __vectors: .word _estack // 0x00 initial SP value .word Reset_Handler // 0x04 reset .word NMI_Handler // 0x08 non-maskable interrupt .word HardFault_Handler// 0x0C hard fault // ... system exceptions ... .word SysTick_Handler // system tick timer .word TIM2_IRQHandler // first device interrupt // ... up to ~240 device IRQs ...

3. Automatic stacking — the magic

When an interrupt fires, the core automatically pushes 8 registers onto the stack: the AAPCS caller-saved set r0–r3, r12, LR, PC, and xPSR. On return it pops them back. Because these are exactly the registers a C function is allowed to clobber, the handler doesn't need any special wrapper:

// A complete, correct Cortex-M interrupt handler — just C: void TIM2_IRQHandler(void) { TIM2->SR &= ~TIM_SR_UIF; // clear the interrupt flag (always!) toggle_led(); }

💡 The valet that parks your state

Classic ARM made you save and restore registers in assembly. The NVIC is like a valet: it parks all the volatile state for you on entry and brings it back on exit. You just write the handler logic — in C.

4. Priorities & preemption

Every interrupt gets a priority number, and the golden rule is counter-intuitive: lower number = higher priority. A higher-priority interrupt can preempt a running lower-priority handler, nesting on top of it; equal-or-lower ones wait.

Priority is split into a preemption field (decides nesting) and a sub-priority field (breaks ties).
The number of priority bits is device-specific (often 3–8 bits → 8–256 levels).
You set it with CMSIS: NVIC_SetPriority(TIM2_IRQn, 2); then NVIC_EnableIRQ(TIM2_IRQn);

5. Tail-chaining & late arrival

The NVIC has two clever latency optimisations:

Feature	What it does
Tail-chaining	If another interrupt is pending when a handler ends, the core skips the pop+push of the stack frame and jumps straight into the next handler.
Late arrival	If a higher-priority interrupt arrives during the stacking of a lower one, the core re-targets to the higher handler without redoing the stacking.

Both eliminate redundant memory traffic, giving Cortex-M its famously deterministic, low interrupt latency — typically a fixed 12 cycles to enter a handler.

6. Special system handlers

SysTick — a simple 24-bit countdown timer in the core, the classic heartbeat for an RTOS scheduler tick.
PendSV — a deliberately lowest-priority, software-pendable exception used by RTOSes to perform context switches safely after all other interrupts finish.
SVC — the supervisor call, the gateway from unprivileged thread code into the OS kernel.

✅ The mental model

The NVIC moves interrupt plumbing into hardware: it vectors directly to your handler, auto-stacks the caller-saved registers (so an ISR is plain C), supports numbered priorities with preemption (lower = higher), and uses tail-chaining for back-to-back interrupts. That's why Cortex-M interrupt handling is both fast and easy.

🎯 Day 18 takeaways

The NVIC is built into every Cortex-M; it vectors, stacks and prioritises in hardware.
The vector table is an array of addresses; slot 0 is the initial SP.
Auto-stacking of r0–r3, r12, LR, PC, xPSR → an ISR is just a C function.
Lower priority number = higher priority; higher ones preempt (nesting).
Tail-chaining / late-arrival cut latency; entry is a deterministic ~12 cycles.

Quick check

Which 8 registers does the NVIC stack automatically, and why those?
Does priority 1 preempt priority 5, or the other way round?
What does tail-chaining save between two back-to-back interrupts?

FAQ

What is the NVIC?

The Nested Vectored Interrupt Controller built into Cortex-M — it handles vectoring, auto-stacking and prioritised, nestable interrupts in hardware.

Why is a Cortex-M ISR just C?

The hardware auto-saves the caller-saved registers (r0–r3, r12, LR, PC, xPSR), so no assembly wrapper is needed.

What is tail-chaining?

Skipping the unstack/restack between back-to-back interrupts, lowering latency.

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