DAY 28 · ADVANCED (64-BIT & BEYOND)

Floating Point — The VFP Unit

Everything so far has been integers. But graphics, physics, audio, scientific code and AI all live in the world of real numbers with fractions — and that needs floating point. Today we'll see how ARM does fractional math in hardware via the VFP/FPU, what IEEE 754 actually stores, and the subtle pitfalls (rounding, denormals, ABIs) that trip up real engineers.

1. Why hardware floating point?

You can do fractional math with integers (fixed-point), and tiny microcontrollers without an FPU must emulate floats in software — slow, hundreds of cycles per operation. A hardware FPU (Floating-Point Unit) executes a float add or multiply in just a few cycles. For any workload heavy in decimals — 3D transforms, DSP, neural nets — a hardware FPU is the difference between smooth and unusable.

On ARM this unit is historically called the VFP (Vector Floating Point). In modern AArch64 it's tightly integrated with NEON (Day 27) — they share the same V register file.

2. IEEE 754 — how a float is stored

Floating point follows the IEEE 754 standard. A number is stored as three fields — a sign, an exponent, and a fraction (mantissa) — essentially scientific notation in binary: value = ±1.fraction × 2^exponent.

Precision	Bits	Sign / Exp / Frac	ARM name
Half	16	1 / 5 / 10	H
Single (float)	32	1 / 8 / 23	S
Double (double)	64	1 / 11 / 52	D

More exponent bits → larger range; more fraction bits → more precision. The standard also defines special values: ±0, ±∞ (infinity), and NaN (Not-a-Number, e.g. from 0/0). Half precision has surged in importance because machine-learning inference often uses 16-bit floats to halve memory and double throughput.

3. The floating-point register file

In AArch64 the FP and NEON units share 32 registers V0–V31. For scalar floating point you access them through width-specific views:

• H0–H31 — 16-bit (half) views
• S0–S31 — 32-bit (single) views
• D0–D31 — 64-bit (double) views
• Q0–Q31 / V0–V31 — the full 128-bit registers used by NEON vectors

So S5, D5 and V5 are the same physical register viewed at different widths — exactly mirroring how X and W share GPRs in Day 26.

Note FMADD — a fused multiply-add computes a*b+c with a single rounding, which is both faster and more accurate than separate multiply then add. It's the backbone of dot products and matrix math.

4. Control & status: FPCR and FPSR

Two special registers govern FP behaviour:

• FPCR (Floating-Point Control Register) — selects the rounding mode and behaviour switches like flush-to-zero for denormals.
• FPSR (Floating-Point Status Register) — sticky exception flags recording whether an operation was inexact, overflowed, underflowed, divided by zero, or was invalid.

Rounding modes

Since results rarely fit exactly, IEEE 754 defines how to round. The FPCR selects one:

• Round to nearest, ties to even — the default and the right choice for almost everything.
• Round toward zero (truncate), toward +∞, toward −∞ — for specialised numeric needs.

Denormals (subnormals)

Numbers extremely close to zero are represented as denormals. They preserve accuracy near zero but can be very slow on some hardware. Performance-critical audio/DSP code often sets flush-to-zero in FPCR, trading a sliver of accuracy for consistent speed.

5. Soft-float vs hard-float — an ABI you must match

This catches many embedded developers. There are two ways floating point reaches the hardware, and they're incompatible ABIs:

	Hard-float	Soft-float
FP ops	real FPU instructions	emulated in software libraries
FP args passed in	FP registers (S/D)	integer registers
Speed	fast	slow
Needs FPU?	yes	no

Every object you link must use the same float ABI — mixing a hard-float library with soft-float code produces subtle, maddening bugs or link errors. On chips with an FPU (all AArch64), hard-float is standard. On the smallest MCUs without an FPU, soft-float is the only option. A middle option, softfp, uses the FPU but passes args in integer registers for compatibility.

6. FP and performance

• Prefer single precision when accuracy allows — half the memory bandwidth and often double the throughput of double precision.
• Use FMA (fused multiply-add) for dot products and polynomials.
• Vectorize with NEON to do multiple floats per instruction (Day 27).
• Watch denormals in DSP; enable flush-to-zero if a tiny accuracy loss is acceptable.
• Avoid needless int↔float conversions in hot loops — they cost cycles.

Quick check

1. Name the three IEEE 754 fields and the three common precisions.
2. Why are S5, D5 and V5 related?
3. What does the FPCR control, and what does the FPSR record?
4. Why must all linked code agree on hard- vs soft-float?

FAQ

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