DAY 26 · ADVANCED (64-BIT & BEYOND)

AArch64 — The 64-bit Register Model

Welcome to Phase 4. Everything you learned in Days 1–25 was mostly the 32-bit world. Now we step into AArch64 — the 64-bit architecture that powers modern phones, Apple Silicon Macs, AWS Graviton servers and the fastest ARM chips on Earth. The good news: it's actually cleaner and simpler than 32-bit ARM. Let's rebuild the programmer's model for 64 bits.

1. Two states: AArch64 and AArch32

ARMv8-A introduced a fundamental split. A core can run in one of two execution states:

• AArch64 — the new 64-bit state, running the A64 instruction set. 64-bit registers, 64-bit addresses, 31 general-purpose registers.
• AArch32 — backward-compatible 32-bit state, running the classic A32 (ARM) and T32 (Thumb) instruction sets you met in earlier lessons.

This is why a single modern chip can still run old 32-bit apps while delivering full 64-bit performance to new ones. Crucially, the state can only change on an exception boundary — you don't flip between 64-bit and 32-bit mid-function the way you interworked ARM and Thumb (Day 16). From here on we focus entirely on AArch64, the state all new software targets.

2. The register file: X0–X30

Here's the headline change. AArch64 gives you 31 general-purpose registers, each 64 bits wide, named X0 through X30. That's nearly double the 16 you had in AArch32 — and more registers means fewer trips to memory, which is a direct performance win.

Every X register has a 32-bit view called W0–W30 that accesses its lower 32 bits. Writing to a W register zeroes the upper 32 bits of the corresponding X register — a deliberate rule that avoids partial-register stalls.

Name	Width	Meaning
X0–X30	64-bit	general-purpose registers
W0–W30	32-bit	lower-half views of X0–X30
XZR / WZR	64/32	the zero register (reads 0, writes discarded)
SP	64-bit	the stack pointer (must stay 16-byte aligned)
PC	64-bit	program counter — not a general-purpose register

3. The clever bit: register 31

You may have noticed the registers stop at 30, not 31. Encoding slot 31 is special — depending on the instruction it means either the zero register (XZR/WZR) or the stack pointer (SP).

• The zero register always reads as 0 and silently discards writes. It's wonderfully handy: comparing against zero, clearing a value, or discarding a result becomes free — no register wasted holding a constant 0.
• The stack pointer is no longer a normal GPR you can accidentally clobber; it has its own role and a strict 16-byte alignment requirement.

4. The PC is no longer a register

In AArch32, the program counter was r15 — a general-purpose register you could read and even write to jump. Powerful, but a security and predictability nightmare. AArch64 removes the PC from the general register file. You can no longer do arithmetic on it or load into it directly; control flow happens only through proper branch instructions. This single change kills a whole class of exploits and makes the pipeline easier to build.

The link register is now X30: a BL (branch with link) saves the return address there, and you return with RET (which defaults to X30). Compare this to the AArch32 BX LR from Day 15.

5. From processor modes to exception levels

The old AArch32 modes (User, IRQ, FIQ, Supervisor…) from Day 5 are gone. AArch64 replaces them with a clean ladder of four Exception Levels:

Level	Runs	Privilege
EL0	applications (user space)	least
EL1	OS kernel (Linux, Android)	↑
EL2	hypervisor (virtualization)	↑↑
EL3	secure monitor (TrustZone, Day 23)	most

Each level (except EL0) has its own banked SP and its own system registers (with the _EL1, _EL2 suffixes you saw in Day 24). Exceptions move you up a level; the ERET instruction returns you down. This maps perfectly onto modern software: app → kernel → hypervisor → secure firmware.

6. PSTATE replaces the CPSR

The single CPSR register from Day 3 is replaced by PSTATE — processor state held as a set of independently accessible fields rather than one packed word. The familiar condition flags live here:

• N, Z, C, V — Negative, Zero, Carry, oVerflow (same meanings as before).
• Interrupt masks (D, A, I, F), the current exception level, and the stack-pointer selector (SPSel).

On taking an exception, PSTATE is saved into SPSR_ELx and the return address into ELR_ELx — the 64-bit equivalent of the banked SPSR/LR mechanism from Day 17.

7. The A64 instruction set — cleaner by design

A64 keeps the RISC spirit but tidies up the quirks:

• Fixed 32-bit instructions — every A64 instruction is exactly 4 bytes (no Thumb mixing within A64).
• No blanket conditional execution. The AArch32 trick of predicating every instruction is gone. Instead you get conditional branches plus efficient conditional select instructions like CSEL, CSET and CSINC that avoid branches without bloating the encoding.
• LDP / STP replace LDM/STM — load or store a pair of registers in one instruction, the workhorse of function prologues/epilogues.
• Larger immediates and PC-relative addressing (ADRP) for the 64-bit address space.

8. The AAPCS64 calling convention

The 64-bit procedure call standard (cf. Day 15's AAPCS) takes full advantage of the larger register file:

Registers	Role	Preserved by
X0–X7	arguments 1–8; X0 = return value	caller-saved
X8	indirect result location	caller-saved
X9–X15	scratch / temporaries	caller-saved
X16–X17	intra-procedure-call (IP0/IP1)	caller-saved
X18	platform register (reserved)	platform
X19–X28	local variables	callee-saved
X29	frame pointer (FP)	callee-saved
X30	link register (LR)	special

With eight argument registers instead of four, most function calls pass everything in registers and never touch the stack — a real speed advantage over AArch32.

9. A glimpse beyond: SVE

AArch64 also opened the door to the Scalable Vector Extension (SVE/SVE2) — a vector instruction set whose register width is not fixed in the program (it can be 128 to 2048 bits depending on the chip), so the same binary scales across implementations. It's huge for HPC and machine learning. We'll meet ARM's mainstream vector engine, NEON, next lesson; SVE is its supercomputer-class cousin.

Quick check

1. How many general-purpose registers does AArch64 have, and what are the two views called?
2. What two things can encoding "register 31" mean?
3. Why is removing the PC from the register file a good thing?
4. Which registers carry the first eight function arguments?

FAQ

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