In Day 1 we said an FPGA "becomes" your circuit. Today we open the lid and see how. The magic comes down to one beautifully simple idea — a tiny memory that pretends to be a logic gate — repeated millions of times and wired together. Understand the LUT and the rest of the FPGA falls into place.
Zoom into an FPGA and you'll see a regular grid: thousands of small logic blocks (the "islands") floating in a sea of programmable routing (the wires between them), with specialised blocks and I/O around the edges. Build a design and you're really doing two things: configuring the logic blocks to compute the functions you need, and configuring the routing to connect them in the right pattern. Let's start with the smallest piece.
A traditional chip builds logic from fixed AND/OR/NOT gates. An FPGA can't — its gates must be reconfigurable. The trick: implement logic with a Look-Up Table (LUT), which is just a tiny memory holding a truth table.
Here's the insight. Any Boolean function of N inputs is completely defined by its truth table — the output for each of the 2N input combinations. So instead of building gates, store those 2N output bits in small memory cells and use the inputs as the address. Whatever bit is stored at the addressed location becomes the output.
0001 and it's an AND gate; load 0111 and it's an OR.That's the whole trick. A 2-input LUT needs 4 memory bits; load 0,0,0,1 and it's an AND gate, load 0,1,1,1 and the same hardware is an OR gate. Change the bits, change the logic — no new silicon. This is exactly why the bitstream (Day 1) can turn the chip into anything.
Real FPGAs use larger LUTs. An N-input LUT stores 2N bits and can implement any function of N inputs:
| LUT size | Memory bits | Implements |
|---|---|---|
| 2-input | 4 | any 2-input function |
| 4-input | 16 | any 4-input function |
| 6-input (modern) | 64 | any 6-input function |
Modern AMD/Xilinx and Intel FPGAs use 6-input LUTs (often splittable into two smaller LUTs). Bigger functions are built by chaining several LUTs through the routing — that's what synthesis figures out for you.
A LUT alone is purely combinational: output depends only on the current inputs, with no memory. Real designs need state — counters, registers, FSMs (recall sequential logic). So every logic cell pairs its LUT with a flip-flop: a one-bit storage element that captures the LUT's output on a clock edge. You can use the LUT output directly (combinational) or registered through the flip-flop (sequential) — the cell can do either.
Group a LUT, a flip-flop, and a little extra hardware and you get the FPGA's repeating unit — often called a logic cell or, in groups, a slice. A typical cell contains:
Several slices are grouped into a CLB (Configurable Logic Block) — the tile that repeats across the entire chip. (Intel calls its equivalent a LAB, Logic Array Block.) When a datasheet says an FPGA has "100K logic cells," it means roughly that many LUT+FF units, packaged into thousands of CLBs. The whole device is a vast 2-D array of these tiles.
Logic blocks are useless unless you can connect them. Between every CLB runs the programmable interconnect: wire segments joined by switch boxes full of configurable switches (pass transistors controlled by SRAM bits). Set the switches and you create whatever connection your design needs.
Routing is a bigger deal than beginners expect:
Addition is everywhere, and rippling a carry through generic LUTs and routing would be slow. So FPGAs add a dedicated carry chain: a fast, hardwired path that passes the carry directly from one cell to the next, vertically up a column, bypassing the general routing. This makes adders and counters far faster than LUTs alone could manage — one reason FPGAs are great at DSP and arithmetic.
You never place LUTs by hand. You write HDL; the synthesis tool converts it to logic and maps that logic onto LUTs, FFs and carry chains. A trivial example:
Try writing small modules in our online Verilog simulator and running synthesis to see how your code turns into gates — the same process the FPGA tools use before mapping to LUTs.
Think of a LUT as a little box with a pre-written answer sheet. You ask it a question (the input combination) and it reads back the pre-decided answer. To make it behave like a different gate, you just rewrite the answer sheet. An FPGA is millions of these answer-sheet boxes plus a giant configurable switchboard connecting them — and the bitstream fills in every answer sheet and sets every switch.
An FPGA is a grid of CLBs in a sea of programmable routing. The atom is the LUT — a tiny SRAM truth table that becomes any logic function of its inputs. Pair it with a flip-flop (for state), a mux and a carry chain (for fast math) to get a logic cell; group cells into slices and CLBs. Routing connects it all — and often decides your speed. The bitstream programs every LUT bit and every routing switch.
A Look-Up Table — a small SRAM storing a function's truth table; the inputs address it and the stored bit is the output, so it can be any N-input gate.
A Configurable Logic Block — a tile of several logic cells (LUT + flip-flop + carry + mux) repeated across the FPGA.
The LUT does combinational logic; the flip-flop stores one bit on a clock edge to give the design state.
The configurable wire network and switch boxes that connect blocks; place-and-route configures it, and it often dominates timing.