The Plan — What We're Going to Build

Welcome to the most hands-on course on the site. Over the coming lessons we won't just learn about a processor — we'll build one, line by line, until it runs real programs. And we'll do it with Claude writing and optimizing the Verilog at every step. Today is the map: what we're building, how, and the full roadmap.

1. The mission

By the end of this course you will have a working RISC-V CPU — a real RV32I processor, written in Verilog, that fetches, decodes and executes genuine RISC-V machine code. Then we go further and optimize it: turn the simple single-cycle design into a 5-stage pipelined core with forwarding and hazard handling, add CSRs and memory-mapped I/O, and even run it on an FPGA.

Crucially, you build it too. Every module — register file, ALU, control unit, datapath, pipeline — is given to you as copyable, downloadable code you can drop straight into our online Verilog simulator and watch run. No black boxes.

2. Why build a CPU from scratch?

You can use computers your whole life and still find the processor "magic." Building one dissolves that mystery forever. You'll finally feel how an instruction becomes electrical control signals, how a register file and ALU cooperate, why pipelining is both powerful and tricky, and what a hazard really is. It's the single best way to understand computer architecture — and a standout portfolio project. Because RISC-V is an open ISA (no licence needed — see RISC-V vs ARM), we're legally free to implement every instruction ourselves, exactly like India's SHAKTI does.

3. RISC-V in plain English (no jargon)

Forget everything intimidating for a moment. Here's the whole idea in one picture:

That "list of commands a chip understands" has a formal name: the ISA — Instruction Set Architecture. It's the language the hardware speaks. Every program — a game, a browser, an OS — is ultimately just a very long sequence of these simple commands. And a CPU's entire life is a four-step loop:

1. Fetch — get the next instruction from memory.
2. Decode — figure out what it's asking ("oh, it's an add").
3. Execute — do it (add the two numbers).
4. Repeat — move to the next instruction.

So what makes RISC-V special among instruction sets? Two things:

• It's "RISC" = Reduced Instruction Set Computer. The commands are deliberately few and simple — each does one tiny job. (The opposite style, CISC, has a few big complicated commands.) Simple commands are easier to build in hardware and easier to make fast — which is exactly why we can build one.
• It's open and free. Anyone — a student, a startup, a country — can use and implement RISC-V without paying a licence or asking permission. ARM and x86 are owned and licensed; RISC-V is like an open, public standard. That's why we're legally allowed to build the whole thing ourselves in this course.

4. What does "RV32I" mean?

"RV32I" looks cryptic but it's just three pieces stuck together. Read it left to right:

• RV → short for RISC-V (the family).
• 32 → it works with 32-bit numbers. Each storage slot ("register") holds a 32-bit value, and memory addresses are 32 bits wide. Think of it as the size of each box of data the CPU handles at once. (There's also RV64 for 64-bit and RV128 — but 32-bit is the perfect size to learn on.)
• I → the base Integer instruction set: the small, mandatory core of about 40 instructions that every RISC-V processor must have. These work only with whole numbers (integers) — no decimals, no built-in multiply yet.

So RV32I = the 32-bit, integer-only foundation of RISC-V. It's small enough to fully understand and build, yet complete enough to run real programs. That's why we start here.

What RV32I actually defines

The "I" base gives us everything we need to compute:

That's it — with just those, you can build loops, if-statements, function calls and any calculation. Anything extra is an optional add-on named by another letter, which RISC-V lets you bolt on only if you need it:

A chip with all the common ones is written RV32IMAFDC — but the I is the heart, and the only part that's mandatory. Master RV32I and you understand the core of every RISC-V processor on Earth, including SHAKTI.

5. What exactly we're building

Our target is a clean, correct, then progressively faster RV32I core. Here's the high-level datapath we'll assemble piece by piece in Phase 2:

6. How Claude builds it

Here's what makes this course different. For each module, Claude designs the architecture, writes clean and commented Verilog, and explains every decision — then progressively optimizes the design (sharing logic, pipelining, removing stalls). You get the reasoning and the ready-to-run code.

Honest scope: this is a genuine, standards-compliant educational RV32I core that executes real RISC-V code and gets real optimizations — not a commercial tape-out-grade CPU. It teaches exactly how production cores (like SHAKTI) are structured, which is the goal.

7. The code format — copy or download every module

You asked for it, so here's the standard for the whole course: every code block has a Copy button and a Download button. Try it on the project's top-level skeleton — the shell we'll fill in across Phase 2:

// EcrioniX · RISC-V from Scratch — top-level core (skeleton)
// We flesh out each piece across Phase 2 (Days 7-15).
module riscv_core (
    input  wire        clk,
    input  wire        rst_n,      // active-low reset
    // simple instruction + data memory interfaces
    output wire [31:0] imem_addr,
    input  wire [31:0] imem_data,
    output wire [31:0] dmem_addr,
    output wire [31:0] dmem_wdata,
    output wire        dmem_we,
    input  wire [31:0] dmem_rdata
);
    // --- coming soon ---
    // wire [31:0] pc;            // Day 8  : program counter
    // wire [31:0] instr;         // Day 8  : fetched instruction
    // regfile / alu / control... // Days 9-14
endmodule

What those ports mean (the CPU's pins)

The lines inside module riscv_core (...) are the chip's ports — its electrical "pins," the only way it talks to the outside world. input = a signal coming into the CPU; output = a signal the CPU drives out. wire [31:0] just means "a 32-bit-wide connection." Let's decode every one:

Two of those names need their full forms — they confuse everyone at first:

• imem = Instruction Memory — the storage that holds your program (the list of instructions). The CPU reads it to fetch each instruction.
• dmem = Data Memory — the storage that holds your data / variables (the numbers the program works on). The CPU reads and writes it during lw (load word) and sw (store word).

So this top-level module is really saying: "Give me the instruction at imem_addr, and let me read/write data at dmem_addr." Everything we build in Phase 2 lives inside this shell and decides what those addresses and data should be each clock tick.

And here's the first program our finished CPU will run — sum the numbers 1 to 10 in RISC-V assembly:

# sum 1..10 -> x10 (a0). Our CPU will execute this by Day 15.
        li   x5, 0          # sum = 0
        li   x6, 1          # i   = 1
        li   x7, 11         # limit
loop:   bge  x6, x7, done   # if i >= 11, stop
        add  x5, x5, x6     # sum += i
        addi x6, x6, 1      # i++
        jal  x0, loop       # repeat
done:   add  x10, x5, x0    # result in a0 (should be 55)

Don't worry if the assembly looks unfamiliar — decoding exactly these instructions is what Phase 1 is about.

8. The roadmap

See the full lesson-by-lesson roadmap →

9. What you'll need

• A browser — that's the only requirement. Every module runs in our online Verilog simulator.
• Basic Verilog — modules, wires/regs, always blocks. New to it? Start with our Verilog tutorials.
• Optional (local): Icarus Verilog / Verilator to simulate offline, and a RISC-V assembler/toolchain if you want to compile your own programs.

Quick check

1. What ISA are we implementing, and what does "RV32I" mean?
2. What's the difference between the v1 and v2 designs we'll build?
3. What does the sum.s program compute, and where's the result?

FAQ

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