On Day 1 we learned ARM is a load/store machine: all real work happens in registers. So today we meet those registers — the CPU's handful of ultra-fast scratchpads — and the status register that records what just happened.
A register is a tiny piece of storage inside the CPU that holds one value (32 bits in classic ARM). Registers are the fastest memory that exists — accessed in a single cycle — which is exactly why ARM insists all arithmetic happens here, not in slow external memory.
The classic 32-bit ARM model gives you 16 registers you can name directly: R0–R15, plus a special status register, the CPSR.
These thirteen hold your variables and intermediate results. The hardware treats them equally, but convention (the AAPCS, coming on Day 15) assigns habits: R0–R3 pass the first arguments to a function and return its result; R4–R11 hold longer-lived variables. Following the convention is what lets your code call other people's code safely.
R13, R14 and R15 are ordinary 32-bit registers given special jobs by the hardware:
| Reg | Name | Job |
|---|---|---|
| R13 | SP — Stack Pointer | Points to the top of the stack (where local data & saved registers live). Day 14. |
| R14 | LR — Link Register | Holds the return address when you call a subroutine, so the CPU knows where to come back to. Day 15. |
| R15 | PC — Program Counter | Holds the address of the instruction being fetched. Change it and you've branched. |
The PC is your finger tracking the current line. The LR is the sticky note you leave when you jump to a footnote, so you can return. The SP marks the top of your stack of bookmarks.
After every operation the CPU records what happened in the CPSR (Current Program Status Register). Its top four bits are the condition flags — the single most important thing to learn today:
| Flag | Name | Set when… |
|---|---|---|
| N | Negative | result's bit 31 = 1 (negative as a signed number) |
| Z | Zero | result is exactly 0 |
| C | Carry | an add carried out, or a subtract did not borrow |
| V | oVerflow | signed overflow occurred |
The other CPSR fields: I and F disable IRQ/FIQ interrupts (Day 17), T selects Thumb vs ARM state (Day 6), and the mode bits set the processor mode (Day 5).
Flags are how a CPU makes decisions. Watch CMP (compare) — it subtracts, throws away the result, and just keeps the flags:
So CMP sets the flags and BEQ reads them. That two-step — set flags, then act on them — is the heart of every if, loop and comparison in machine code. We'll build on it heavily in Day 11 (conditional execution).
Registers = the CPU's hands (work happens here). SP / LR / PC = three hands with a permanent job. The CPSR flags (N Z C V) = a sticky note saying what the last result looked like, which the next instruction can read to make a decision.
Everything above is the classic 32-bit (AArch32) model. The 64-bit world (AArch64, Day 26) expands this to 31 general-purpose 64-bit registers, X0–X30, and splits the status flags into their own register. The ideas — registers, SP, return address, NZCV flags — carry straight over.
CMP R0, R1, which flag is set if R0 == R1?Classic 32-bit ARM exposes 16 registers (R0–R15) plus the CPSR. AArch64 has 31 general-purpose registers (X0–X30).
R13 = Stack Pointer, R14 = Link Register (return address), R15 = Program Counter (address being fetched).
The four CPSR condition flags: Negative, Zero, Carry, oVerflow — set by arithmetic/logic results and tested by conditional instructions.