DAY 19 · SYSTEM & MEMORY

The Memory Map & Buses — AHB, APB & AXI

A processor is useless alone. It must reach flash, RAM, a UART, a timer, a GPIO. How? Through one flat address space and a set of on-chip buses. Today you'll see how ARM wires a whole system together with the AMBA bus family — and why there are three different buses, not one.

1. One address space: the memory map

ARM uses a single, flat 32-bit address space (4 GB of addresses). Everything lives somewhere in it: code, data, and peripherals. That last part is the key idea — memory-mapped I/O. There are no special "in/out" instructions like on x86; a peripheral register is just an address, and you control hardware with ordinary LDR/STR.

Cortex-M even standardises the broad layout: code at the bottom, SRAM next, a peripheral region, then private core space (where the NVIC lives) near the top.

2. AMBA: ARM's on-chip bus family

The wires connecting the core to all those addresses follow AMBA (Advanced Microcontroller Bus Architecture) — ARM's royalty-free on-chip interconnect standards. The three you must know:

Bus	Stands for	Built for
APB	Advanced Peripheral Bus	simple, low-power, slow peripherals
AHB	Advanced High-performance Bus	memory & high-bandwidth components
AXI	Advanced eXtensible Interface	high-performance, multi-master SoCs

3. APB — simple and cheap

APB is deliberately minimal: no pipelining, no bursts, single transfers, low gate count and low power. Perfect for a timer, UART, SPI or GPIO block that's never the bottleneck. Each transfer has a simple setup then access phase (the PSEL/PENABLE/PREADY handshake). If you've used our Register-Map Generator or AXI-to-APB bridge, that's APB on the peripheral side.

4. AHB — the fast lane

AHB is pipelined (address phase of the next transfer overlaps the data phase of the current one) and supports burst transfers, giving much higher throughput. It's used for the things that are on the critical path: flash, SRAM, the memory controller, DMA, a USB or Ethernet block. A Cortex-M typically has an AHB-based bus matrix at its heart.

5. AXI — high performance

AXI is the heavyweight, used in application-class (Cortex-A) SoCs. Its defining features:

• Five independent channels — separate read-address, read-data, write-address, write-data, and write-response — so reads and writes proceed in parallel.
• Burst transfers and multiple outstanding transactions (issue many before any completes).
• Out-of-order completion — responses can return in a different order than issued, hiding latency.

That parallelism is why AXI feeds DDR controllers, GPUs and large interconnects where bandwidth is everything.

6. Bridges & the bus matrix

You don't put a slow UART on a fast AXI bus — you'd waste the bus. Instead, a bridge connects bus domains: it's a slave on the fast side and a master on the slow side, translating one protocol to the other.

The bus matrix (or interconnect) is the crossbar that lets multiple masters (CPU, DMA) reach multiple slaves (RAM, peripherals) — ideally in parallel when they target different slaves. This whole structure is what the SoC integration world spends its days assembling.

Quick check

1. What is memory-mapped I/O, and how do you "use" a peripheral with it?
2. Which bus would you put a UART on, and which a DDR controller?
3. What makes AXI able to overlap reads and writes?

FAQ

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