VLSI Design

Clock Domain Crossing

FIFO Depth Calculation

SystemVerilog Data Types (Logic, Bit, Byte)

D Flip Flop Internals

DFT SCAN CHAINS

CLOCK GATING ICG RESET SYNCHRONIZER Clock Muxing

CLOCK TREE SYNTHESIS

Power Gating and Sleep Transistors

CMOS Structure Lab

Static Timing Analysis (STA)

What is Moore’s Law?

CMOS Inverter Design & Operation

Layout Design Rules (DRC & LVS)

Shift Registers (SISO, SIPO, PISO, PIPO)

Gate Level Netlist Explained

Latch vs. Flip-Flop

Finite State Machines (FSM): Mealy vs. Moore

Barrel Shifter Circuit

Clock Dividers (Divide by 2, 4, N)

Phase Locked Loop (PLL) Architecture

Current Mirror Circuits (Basic & Wilson)

Linear Feedback Shift Register

UVM Sequencer, Driver, and Monitor

Async FIFO Design Lab

Binary Gray Code Conversion

AMBA APB Protocol

THE SILICON TRAP

Low Power RTL Design